memtest-ruby.py (9826:014ff1fbff6d) memtest-ruby.py (9827:f47274776aa0)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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75
76# overwrite options.num_cpus with the nb_cores value
77options.num_cpus = nb_cores
78
79# system simulated
80system = System(cpu = cpus,
81 funcmem = SimpleMemory(in_addr_map = False),
82 physmem = SimpleMemory(null = True),
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 66 unchanged lines hidden (view full) ---

75
76# overwrite options.num_cpus with the nb_cores value
77options.num_cpus = nb_cores
78
79# system simulated
80system = System(cpu = cpus,
81 funcmem = SimpleMemory(in_addr_map = False),
82 physmem = SimpleMemory(null = True),
83 funcbus = NoncoherentBus(),
84 clk_domain = SrcClockDomain(clock = options.sys_clock))
83 funcbus = NoncoherentBus())
84# Dummy voltage domain for all our clock domains
85system.voltage_domain = VoltageDomain()
86system.clk_domain = SrcClockDomain(clock = '1GHz',
87 voltage_domain = system.voltage_domain)
85
86# Create a seperate clock domain for components that should run at
87# CPUs frequency
88
89# Create a seperate clock domain for components that should run at
90# CPUs frequency
88system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
91system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
92 voltage_domain = system.voltage_domain)
89
90# All cpus are associated with cpu_clk_domain
91for cpu in cpus:
92 cpu.clk_domain = system.cpu_clk_domain
93
94system.mem_ranges = AddrRange('256MB')
95
96Ruby.create_system(options, system)
97
98# Create a separate clock domain for Ruby
93
94# All cpus are associated with cpu_clk_domain
95for cpu in cpus:
96 cpu.clk_domain = system.cpu_clk_domain
97
98system.mem_ranges = AddrRange('256MB')
99
100Ruby.create_system(options, system)
101
102# Create a separate clock domain for Ruby
99system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
103system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
104 voltage_domain = system.voltage_domain)
100
101assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
102
103for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
104 #
105 # Tie the cpu test and functional ports to the ruby cpu ports and
106 # physmem, respectively
107 #

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106assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
107
108for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
109 #
110 # Tie the cpu test and functional ports to the ruby cpu ports and
111 # physmem, respectively
112 #

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