memtest-ruby.py (9113:9a72589ce4fd) memtest-ruby.py (9120:48eeef8a0997)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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74 for i in xrange(nb_cores) ]
75
76# overwrite options.num_cpus with the nb_cores value
77options.num_cpus = nb_cores
78
79# system simulated
80system = System(cpu = cpus,
81 funcmem = SimpleMemory(in_addr_map = False),
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 65 unchanged lines hidden (view full) ---

74 for i in xrange(nb_cores) ]
75
76# overwrite options.num_cpus with the nb_cores value
77options.num_cpus = nb_cores
78
79# system simulated
80system = System(cpu = cpus,
81 funcmem = SimpleMemory(in_addr_map = False),
82 funcbus = NoncoherentBus(),
82 physmem = SimpleMemory())
83
84Ruby.create_system(options, system)
85
86assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
87
88for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
89 #
90 # Tie the cpu test and functional ports to the ruby cpu ports and
91 # physmem, respectively
92 #
93 cpus[i].test = ruby_port.slave
83 physmem = SimpleMemory())
84
85Ruby.create_system(options, system)
86
87assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
88
89for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
90 #
91 # Tie the cpu test and functional ports to the ruby cpu ports and
92 # physmem, respectively
93 #
94 cpus[i].test = ruby_port.slave
94 cpus[i].functional = system.funcmem.port
95 cpus[i].functional = system.funcbus.slave
95
96 #
97 # Since the memtester is incredibly bursty, increase the deadlock
98 # threshold to 1 million cycles
99 #
100 ruby_port.deadlock_threshold = 1000000
101
102 #
103 # Ruby doesn't need the backing image of memory when running with
104 # the tester.
105 #
106 ruby_port.access_phys_mem = False
107
96
97 #
98 # Since the memtester is incredibly bursty, increase the deadlock
99 # threshold to 1 million cycles
100 #
101 ruby_port.deadlock_threshold = 1000000
102
103 #
104 # Ruby doesn't need the backing image of memory when running with
105 # the tester.
106 #
107 ruby_port.access_phys_mem = False
108
109# connect reference memory to funcbus
110system.funcmem.port = system.funcbus.master
111
108# -----------------------
109# run simulation
110# -----------------------
111
112root = Root(full_system = False, system = system)
113root.system.mem_mode = 'timing'
114
115# Not much point in this being higher than the L1 latency
116m5.ticks.setGlobalFrequency('1ns')
112# -----------------------
113# run simulation
114# -----------------------
115
116root = Root(full_system = False, system = system)
117root.system.mem_mode = 'timing'
118
119# Not much point in this being higher than the L1 latency
120m5.ticks.setGlobalFrequency('1ns')