memtest-ruby.py (10524:fff17530cef6) memtest-ruby.py (10688:22452667fd5c)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 56 unchanged lines hidden (view full) ---

65options.l2_assoc=2
66options.l3_assoc=2
67options.ports=32
68
69#MAX CORES IS 8 with the fals sharing method
70nb_cores = 8
71
72# ruby does not support atomic, functional, or uncacheable accesses
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 56 unchanged lines hidden (view full) ---

65options.l2_assoc=2
66options.l3_assoc=2
67options.ports=32
68
69#MAX CORES IS 8 with the fals sharing method
70nb_cores = 8
71
72# ruby does not support atomic, functional, or uncacheable accesses
73cpus = [ MemTest(atomic=False, percent_functional=50,
73cpus = [ MemTest(percent_functional=50,
74 percent_uncacheable=0, suppress_func_warnings=True) \
75 for i in xrange(nb_cores) ]
76
77# overwrite options.num_cpus with the nb_cores value
78options.num_cpus = nb_cores
79
80# system simulated
74 percent_uncacheable=0, suppress_func_warnings=True) \
75 for i in xrange(nb_cores) ]
76
77# overwrite options.num_cpus with the nb_cores value
78options.num_cpus = nb_cores
79
80# system simulated
81system = System(cpu = cpus,
82 funcmem = SimpleMemory(in_addr_map = False),
83 funcbus = NoncoherentXBar())
81system = System(cpu = cpus)
84# Dummy voltage domain for all our clock domains
85system.voltage_domain = VoltageDomain()
86system.clk_domain = SrcClockDomain(clock = '1GHz',
87 voltage_domain = system.voltage_domain)
88
89# Create a seperate clock domain for components that should run at
90# CPUs frequency
91system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',

--- 10 unchanged lines hidden (view full) ---

102# Create a separate clock domain for Ruby
103system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
104 voltage_domain = system.voltage_domain)
105
106assert(len(cpus) == len(system.ruby._cpu_ports))
107
108for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
109 #
82# Dummy voltage domain for all our clock domains
83system.voltage_domain = VoltageDomain()
84system.clk_domain = SrcClockDomain(clock = '1GHz',
85 voltage_domain = system.voltage_domain)
86
87# Create a seperate clock domain for components that should run at
88# CPUs frequency
89system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',

--- 10 unchanged lines hidden (view full) ---

100# Create a separate clock domain for Ruby
101system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
102 voltage_domain = system.voltage_domain)
103
104assert(len(cpus) == len(system.ruby._cpu_ports))
105
106for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
107 #
110 # Tie the cpu test and functional ports to the ruby cpu ports and
108 # Tie the cpu port to the ruby cpu ports and
111 # physmem, respectively
112 #
109 # physmem, respectively
110 #
113 cpus[i].test = ruby_port.slave
114 cpus[i].functional = system.funcbus.slave
115
111 cpus[i].port = ruby_port.slave
112
116 #
117 # Since the memtester is incredibly bursty, increase the deadlock
118 # threshold to 1 million cycles
119 #
120 ruby_port.deadlock_threshold = 1000000
121
113 #
114 # Since the memtester is incredibly bursty, increase the deadlock
115 # threshold to 1 million cycles
116 #
117 ruby_port.deadlock_threshold = 1000000
118
122# connect reference memory to funcbus
123system.funcmem.port = system.funcbus.master
124
125# -----------------------
126# run simulation
127# -----------------------
128
129root = Root(full_system = False, system = system)
130root.system.mem_mode = 'timing'
131
132# Not much point in this being higher than the L1 latency
133m5.ticks.setGlobalFrequency('1ns')
119# -----------------------
120# run simulation
121# -----------------------
122
123root = Root(full_system = False, system = system)
124root.system.mem_mode = 'timing'
125
126# Not much point in this being higher than the L1 latency
127m5.ticks.setGlobalFrequency('1ns')