memtest-ruby.py (10519:7a3ad4b09ce4) memtest-ruby.py (10524:fff17530cef6)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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75 for i in xrange(nb_cores) ]
76
77# overwrite options.num_cpus with the nb_cores value
78options.num_cpus = nb_cores
79
80# system simulated
81system = System(cpu = cpus,
82 funcmem = SimpleMemory(in_addr_map = False),
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 66 unchanged lines hidden (view full) ---

75 for i in xrange(nb_cores) ]
76
77# overwrite options.num_cpus with the nb_cores value
78options.num_cpus = nb_cores
79
80# system simulated
81system = System(cpu = cpus,
82 funcmem = SimpleMemory(in_addr_map = False),
83 physmem = SimpleMemory(null = True),
84 funcbus = NoncoherentXBar())
85# Dummy voltage domain for all our clock domains
86system.voltage_domain = VoltageDomain()
87system.clk_domain = SrcClockDomain(clock = '1GHz',
88 voltage_domain = system.voltage_domain)
89
90# Create a seperate clock domain for components that should run at
91# CPUs frequency

--- 43 unchanged lines hidden --- 		83 funcbus = NoncoherentXBar())
84# Dummy voltage domain for all our clock domains
85system.voltage_domain = VoltageDomain()
86system.clk_domain = SrcClockDomain(clock = '1GHz',
87 voltage_domain = system.voltage_domain)
88
89# Create a seperate clock domain for components that should run at
90# CPUs frequency

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