1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2010 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 77 unchanged lines hidden (view full) --- 86# Create a seperate clock domain for components that should run at 87# CPUs frequency 88system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') 89 90# All cpus are associated with cpu_clk_domain 91for cpu in cpus: 92 cpu.clk_domain = system.cpu_clk_domain 93 |
94system.mem_ranges = AddrRange('256MB') 95 |
96Ruby.create_system(options, system) 97 98# Create a separate clock domain for Ruby 99system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 100 101assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 102 103for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): --- 25 unchanged lines hidden --- |