1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2010 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 65 unchanged lines hidden (view full) --- 74 for i in xrange(nb_cores) ] 75 76# overwrite options.num_cpus with the nb_cores value 77options.num_cpus = nb_cores 78 79# system simulated 80system = System(cpu = cpus, 81 funcmem = SimpleMemory(in_addr_map = False), |
82 physmem = SimpleMemory(null = True), 83 funcbus = NoncoherentBus()) |
84 85Ruby.create_system(options, system) 86 87assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 88 89for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): 90 # 91 # Tie the cpu test and functional ports to the ruby cpu ports and 92 # physmem, respectively 93 # 94 cpus[i].test = ruby_port.slave 95 cpus[i].functional = system.funcbus.slave 96 97 # 98 # Since the memtester is incredibly bursty, increase the deadlock 99 # threshold to 1 million cycles 100 # 101 ruby_port.deadlock_threshold = 1000000 102 |
103# connect reference memory to funcbus 104system.funcmem.port = system.funcbus.master 105 106# ----------------------- 107# run simulation 108# ----------------------- 109 110root = Root(full_system = False, system = system) 111root.system.mem_mode = 'timing' 112 113# Not much point in this being higher than the L1 latency 114m5.ticks.setGlobalFrequency('1ns') |