1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2010 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 95 unchanged lines hidden (view full) --- 104 ruby_port.deadlock_threshold = 1000000 105 106 # 107 # Ruby doesn't need the backing image of memory when running with 108 # the tester. 109 # 110 ruby_port.access_phys_mem = False 111 |
112 113# Connect the system port for loading of binaries etc 114system.system_port = system.ruby._sys_port_proxy.port 115 |
116# ----------------------- 117# run simulation 118# ----------------------- 119 |
120root = Root(full_system = False, system = system) |
121root.system.mem_mode = 'timing' 122 123# Not much point in this being higher than the L1 latency 124m5.ticks.setGlobalFrequency('1ns') |