1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29import m5 30from m5.objects import * 31 32 33#MAX CORES IS 8 with the fals sharing method 34nb_cores = 8 35cpus = [ MemTest() for i in xrange(nb_cores) ] 36 |
37import ruby_config 38ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores) 39 |
40# system simulated 41system = System(cpu = cpus, funcmem = PhysicalMemory(), |
42 physmem = ruby_memory, |
43 membus = Bus(clock="500GHz", width=16)) 44 45for cpu in cpus: 46 cpu.test = system.membus.port 47 cpu.functional = system.funcmem.port 48 49system.physmem.port = system.membus.port 50 51# ----------------------- 52# run simulation 53# ----------------------- 54 55root = Root(system = system) 56root.system.mem_mode = 'timing' |