1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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91
92for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
93 #
94 # Tie the cpu test and functional ports to the ruby cpu ports and
95 # physmem, respectively
96 #
97 cpus[i].test = ruby_port.port
98 cpus[i].functional = system.funcmem.port
99
100# -----------------------
101# run simulation
102# -----------------------
103
104root = Root(system = system)
105root.system.mem_mode = 'timing'
106
107# Not much point in this being higher than the L1 latency
108m5.ticks.setGlobalFrequency('1ns')