1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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29import m5
30from m5.objects import *
31
32
33#MAX CORES IS 8 with the fals sharing method
34nb_cores = 8
35cpus = [ MemTest() for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus, funcmem = PhysicalMemory(),
39 physmem = RubyMemory(num_cpus=nb_cores),
40 membus = Bus(clock="500GHz", width=16))
41
42for cpu in cpus:
43 cpu.test = system.membus.port
44 cpu.functional = system.funcmem.port
45
46system.physmem.port = system.membus.port
47
48# -----------------------
49# run simulation
50# -----------------------
51
52root = Root(system = system)
53root.system.mem_mode = 'timing'