48
49########################## Script Options ########################
50def setOption(parser, opt_str, value = 1):
51 # check to make sure the option actually exists
52 if not parser.has_option(opt_str):
53 raise Exception("cannot find %s in list of possible options" % opt_str)
54
55 opt = parser.get_option(opt_str)
56 # set the value
57 exec("parser.values.%s = %s" % (opt.dest, value))
58
59def getOption(parser, opt_str):
60 # check to make sure the option actually exists
61 if not parser.has_option(opt_str):
62 raise Exception("cannot find %s in list of possible options" % opt_str)
63
64 opt = parser.get_option(opt_str)
65 # get the value
66 exec("return_value = parser.values.%s" % opt.dest)
67 return return_value
68
69def run_test(root):
70 """gpu test requires a specialized run_test implementation to set up the
71 mmio space."""
72
73 # instantiate configuration
74 m5.instantiate()
75
76 # Now that the system has been constructed, setup the mmio space
77 root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096)
78
79 # simulate until program terminates
80 exit_event = m5.simulate(maxtick)
81 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
82
83parser = optparse.OptionParser()
84Options.addCommonOptions(parser)
85Options.addSEOptions(parser)
86
87parser.add_option("-k", "--kernel-files",
88 help="file(s) containing GPU kernel code (colon separated)")
89parser.add_option("-u", "--num-compute-units", type="int", default=2,
90 help="number of GPU compute units"),
91parser.add_option("--num-cp", type="int", default=0,
92 help="Number of GPU Command Processors (CP)")
93parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
94 "per CU")
95parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \
96 "sharing an SQC (icache, and thus icache TLB)")
97parser.add_option("--wf-size", type="int", default=64,
98 help="Wavefront size(in workitems)")
99parser.add_option("--wfs-per-simd", type="int", default=8, help="Number of " \
100 "WF slots per SIMD")
101parser.add_option("--sp-bypass-path-length", type="int", default=4, \
102 help="Number of stages of bypass path in vector ALU for Single "\
103 "Precision ops")
104parser.add_option("--dp-bypass-path-length", type="int", default=4, \
105 help="Number of stages of bypass path in vector ALU for Double "\
106 "Precision ops")
107parser.add_option("--issue-period", type="int", default=4, \
108 help="Number of cycles per vector instruction issue period")
109parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \
110 help="VGPR to Coalescer (Global Memory) data bus width in bytes")
111parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \
112 help="Coalescer to VGPR (Global Memory) data bus width in bytes")
113parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \
114 help="Number of Shared Memory pipelines per CU")
115parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \
116 help="Number of Global Memory pipelines per CU")
117parser.add_option("--vreg-file-size", type="int", default=2048,
118 help="number of physical vector registers per SIMD")
119parser.add_option("--bw-scalor", type="int", default=0,
120 help="bandwidth scalor for scalability analysis")
121parser.add_option("--CPUClock", type="string", default="2GHz",
122 help="CPU clock")
123parser.add_option("--GPUClock", type="string", default="1GHz",
124 help="GPU clock")
125parser.add_option("--cpu-voltage", action="store", type="string",
126 default='1.0V',
127 help = """CPU voltage domain""")
128parser.add_option("--gpu-voltage", action="store", type="string",
129 default='1.0V',
130 help = """CPU voltage domain""")
131parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST",
132 help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)")
133parser.add_option("--xact-cas-mode", action="store_true",
134 help="enable load_compare mode (transactional CAS)")
135parser.add_option("--SegFaultDebug",action="store_true",
136 help="checks for GPU seg fault before TLB access")
137parser.add_option("--LocalMemBarrier",action="store_true",
138 help="Barrier does not wait for writethroughs to complete")
139parser.add_option("--countPages", action="store_true",
140 help="Count Page Accesses and output in per-CU output files")
141parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\
142 "TLBs")
143parser.add_option("--pf-type", type="string", help="type of prefetch: "\
144 "PF_CU, PF_WF, PF_PHASE, PF_STRIDE")
145parser.add_option("--pf-stride", type="int", help="set prefetch stride")
146parser.add_option("--numLdsBanks", type="int", default=32,
147 help="number of physical banks per LDS module")
148parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
149 help="number of cycles per LDS bank conflict")
150
151# Add the ruby specific and protocol specific options
152Ruby.define_options(parser)
153
154GPUTLBOptions.tlb_options(parser)
155
156(options, args) = parser.parse_args()
157
158# The GPU cache coherence protocols only work with the backing store
159setOption(parser, "--access-backing-store")
160
161# Currently, the sqc (I-Cache of GPU) is shared by
162# multiple compute units(CUs). The protocol works just fine
163# even if sqc is not shared. Overriding this option here
164# so that the user need not explicitly set this (assuming
165# sharing sqc is the common usage)
166n_cu = options.num_compute_units
167num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc))
168options.num_sqc = num_sqc # pass this to Ruby
169
170########################## Creating the GPU system ########################
171# shader is the GPU
172shader = Shader(n_wf = options.wfs_per_simd,
173 clk_domain = SrcClockDomain(
174 clock = options.GPUClock,
175 voltage_domain = VoltageDomain(
176 voltage = options.gpu_voltage)),
177 timing = True)
178
179# GPU_RfO(Read For Ownership) implements SC/TSO memory model.
180# Other GPU protocols implement release consistency at GPU side.
181# So, all GPU protocols other than GPU_RfO should make their writes
182# visible to the global memory and should read from global memory
183# during kernal boundary. The pipeline initiates(or do not initiate)
184# the acquire/release operation depending on this impl_kern_boundary_sync
185# flag. This flag=true means pipeline initiates a acquire/release operation
186# at kernel boundary.
187if buildEnv['PROTOCOL'] == 'GPU_RfO':
188 shader.impl_kern_boundary_sync = False
189else:
190 shader.impl_kern_boundary_sync = True
191
192# Switching off per-lane TLB by default
193per_lane = False
194if options.TLB_config == "perLane":
195 per_lane = True
196
197# List of compute units; one GPU can have multiple compute units
198compute_units = []
199for i in xrange(n_cu):
200 compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
201 num_SIMDs = options.simds_per_cu,
202 wfSize = options.wf_size,
203 spbypass_pipe_length = \
204 options.sp_bypass_path_length,
205 dpbypass_pipe_length = \
206 options.dp_bypass_path_length,
207 issue_period = options.issue_period,
208 coalescer_to_vrf_bus_width = \
209 options.glbmem_rd_bus_width,
210 vrf_to_coalescer_bus_width = \
211 options.glbmem_wr_bus_width,
212 num_global_mem_pipes = \
213 options.glb_mem_pipes_per_cu,
214 num_shared_mem_pipes = \
215 options.shr_mem_pipes_per_cu,
216 n_wf = options.wfs_per_simd,
217 execPolicy = options.CUExecPolicy,
218 xactCasMode = options.xact_cas_mode,
219 debugSegFault = options.SegFaultDebug,
220 functionalTLB = True,
221 localMemBarrier = options.LocalMemBarrier,
222 countPages = options.countPages,
223 localDataStore = \
224 LdsState(banks = options.numLdsBanks,
225 bankConflictPenalty = \
226 options.ldsBankConflictPenalty)))
227 wavefronts = []
228 vrfs = []
229 for j in xrange(options.simds_per_cu):
230 for k in xrange(shader.n_wf):
231 wavefronts.append(Wavefront(simdId = j, wf_slot_id = k))
232 vrfs.append(VectorRegisterFile(simd_id=j,
233 num_regs_per_simd=options.vreg_file_size))
234 compute_units[-1].wavefronts = wavefronts
235 compute_units[-1].vector_register_file = vrfs
236 if options.TLB_prefetch:
237 compute_units[-1].prefetch_depth = options.TLB_prefetch
238 compute_units[-1].prefetch_prev_type = options.pf_type
239
240 # attach the LDS and the CU to the bus (actually a Bridge)
241 compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave
242 compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort
243
244# Attach compute units to GPU
245shader.CUs = compute_units
246
247# this is a uniprocessor only test, thus the shader is the second index in the
248# list of "system.cpus"
249options.num_cpus = 1
250shader_idx = 1
251cpu = TimingSimpleCPU(cpu_id=0)
252
253########################## Creating the GPU dispatcher ########################
254# Dispatcher dispatches work from host CPU to GPU
255host_cpu = cpu
256dispatcher = GpuDispatcher()
257
258# Currently does not test for command processors
259cpu_list = [cpu] + [shader] + [dispatcher]
260
261system = System(cpu = cpu_list,
262 mem_ranges = [AddrRange(options.mem_size)],
263 mem_mode = 'timing')
264
265# Dummy voltage domain for all our clock domains
266system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
267system.clk_domain = SrcClockDomain(clock = '1GHz',
268 voltage_domain = system.voltage_domain)
269
270# Create a seperate clock domain for components that should run at
271# CPUs frequency
272system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz',
273 voltage_domain = \
274 system.voltage_domain)
275
276# configure the TLB hierarchy
277GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx)
278
279# create Ruby system
280system.piobus = IOXBar(width=32, response_latency=0,
281 frontend_latency=0, forward_latency=0)
282Ruby.create_system(options, None, system)
283
284# Create a separate clock for Ruby
285system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
286 voltage_domain = system.voltage_domain)
287
288# create the interrupt controller
289cpu.createInterruptController()
290
291#
292# Tie the cpu cache ports to the ruby cpu ports and
293# physmem, respectively
294#
295cpu.connectAllPorts(system.ruby._cpu_ports[0])
296system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave
297
298# attach CU ports to Ruby
299# Because of the peculiarities of the CP core, you may have 1 CPU but 2
300# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be
301# hooked up until after the CP. To make this script generic, figure out
302# the index as below, but note that this assumes there is one sequencer
303# per compute unit and one sequencer per SQC for the math to work out
304# correctly.
305gpu_port_idx = len(system.ruby._cpu_ports) \
306 - options.num_compute_units - options.num_sqc
307gpu_port_idx = gpu_port_idx - options.num_cp * 2
308
309wavefront_size = options.wf_size
310for i in xrange(n_cu):
311 # The pipeline issues wavefront_size number of uncoalesced requests
312 # in one GPU issue cycle. Hence wavefront_size mem ports.
313 for j in xrange(wavefront_size):
314 system.cpu[shader_idx].CUs[i].memory_port[j] = \
315 system.ruby._cpu_ports[gpu_port_idx].slave[j]
316 gpu_port_idx += 1
317
318for i in xrange(n_cu):
319 if i > 0 and not i % options.cu_per_sqc:
320 gpu_port_idx += 1
321 system.cpu[shader_idx].CUs[i].sqc_port = \
322 system.ruby._cpu_ports[gpu_port_idx].slave
323gpu_port_idx = gpu_port_idx + 1
324
325# Current regression tests do not support the command processor
326assert(options.num_cp == 0)
327
328# connect dispatcher to the system.piobus
329dispatcher.pio = system.piobus.master
330dispatcher.dma = system.piobus.slave
331
332################# Connect the CPU and GPU via GPU Dispatcher ###################
333# CPU rings the GPU doorbell to notify a pending task
334# using this interface.
335# And GPU uses this interface to notify the CPU of task completion
336# The communcation happens through emulated driver.
337
338# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array
339# parameters must be after the explicit setting of the System cpu list
340shader.cpu_pointer = host_cpu
341dispatcher.cpu = host_cpu
342dispatcher.shader_pointer = shader
343
344# -----------------------
345# run simulation
346# -----------------------
347
348root = Root(full_system = False, system = system)
349m5.ticks.setGlobalFrequency('1THz')
350root.system.mem_mode = 'timing'
| 47
48########################## Script Options ########################
49def setOption(parser, opt_str, value = 1):
50 # check to make sure the option actually exists
51 if not parser.has_option(opt_str):
52 raise Exception("cannot find %s in list of possible options" % opt_str)
53
54 opt = parser.get_option(opt_str)
55 # set the value
56 exec("parser.values.%s = %s" % (opt.dest, value))
57
58def getOption(parser, opt_str):
59 # check to make sure the option actually exists
60 if not parser.has_option(opt_str):
61 raise Exception("cannot find %s in list of possible options" % opt_str)
62
63 opt = parser.get_option(opt_str)
64 # get the value
65 exec("return_value = parser.values.%s" % opt.dest)
66 return return_value
67
68def run_test(root):
69 """gpu test requires a specialized run_test implementation to set up the
70 mmio space."""
71
72 # instantiate configuration
73 m5.instantiate()
74
75 # Now that the system has been constructed, setup the mmio space
76 root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096)
77
78 # simulate until program terminates
79 exit_event = m5.simulate(maxtick)
80 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
81
82parser = optparse.OptionParser()
83Options.addCommonOptions(parser)
84Options.addSEOptions(parser)
85
86parser.add_option("-k", "--kernel-files",
87 help="file(s) containing GPU kernel code (colon separated)")
88parser.add_option("-u", "--num-compute-units", type="int", default=2,
89 help="number of GPU compute units"),
90parser.add_option("--num-cp", type="int", default=0,
91 help="Number of GPU Command Processors (CP)")
92parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
93 "per CU")
94parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \
95 "sharing an SQC (icache, and thus icache TLB)")
96parser.add_option("--wf-size", type="int", default=64,
97 help="Wavefront size(in workitems)")
98parser.add_option("--wfs-per-simd", type="int", default=8, help="Number of " \
99 "WF slots per SIMD")
100parser.add_option("--sp-bypass-path-length", type="int", default=4, \
101 help="Number of stages of bypass path in vector ALU for Single "\
102 "Precision ops")
103parser.add_option("--dp-bypass-path-length", type="int", default=4, \
104 help="Number of stages of bypass path in vector ALU for Double "\
105 "Precision ops")
106parser.add_option("--issue-period", type="int", default=4, \
107 help="Number of cycles per vector instruction issue period")
108parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \
109 help="VGPR to Coalescer (Global Memory) data bus width in bytes")
110parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \
111 help="Coalescer to VGPR (Global Memory) data bus width in bytes")
112parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \
113 help="Number of Shared Memory pipelines per CU")
114parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \
115 help="Number of Global Memory pipelines per CU")
116parser.add_option("--vreg-file-size", type="int", default=2048,
117 help="number of physical vector registers per SIMD")
118parser.add_option("--bw-scalor", type="int", default=0,
119 help="bandwidth scalor for scalability analysis")
120parser.add_option("--CPUClock", type="string", default="2GHz",
121 help="CPU clock")
122parser.add_option("--GPUClock", type="string", default="1GHz",
123 help="GPU clock")
124parser.add_option("--cpu-voltage", action="store", type="string",
125 default='1.0V',
126 help = """CPU voltage domain""")
127parser.add_option("--gpu-voltage", action="store", type="string",
128 default='1.0V',
129 help = """CPU voltage domain""")
130parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST",
131 help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)")
132parser.add_option("--xact-cas-mode", action="store_true",
133 help="enable load_compare mode (transactional CAS)")
134parser.add_option("--SegFaultDebug",action="store_true",
135 help="checks for GPU seg fault before TLB access")
136parser.add_option("--LocalMemBarrier",action="store_true",
137 help="Barrier does not wait for writethroughs to complete")
138parser.add_option("--countPages", action="store_true",
139 help="Count Page Accesses and output in per-CU output files")
140parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\
141 "TLBs")
142parser.add_option("--pf-type", type="string", help="type of prefetch: "\
143 "PF_CU, PF_WF, PF_PHASE, PF_STRIDE")
144parser.add_option("--pf-stride", type="int", help="set prefetch stride")
145parser.add_option("--numLdsBanks", type="int", default=32,
146 help="number of physical banks per LDS module")
147parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
148 help="number of cycles per LDS bank conflict")
149
150# Add the ruby specific and protocol specific options
151Ruby.define_options(parser)
152
153GPUTLBOptions.tlb_options(parser)
154
155(options, args) = parser.parse_args()
156
157# The GPU cache coherence protocols only work with the backing store
158setOption(parser, "--access-backing-store")
159
160# Currently, the sqc (I-Cache of GPU) is shared by
161# multiple compute units(CUs). The protocol works just fine
162# even if sqc is not shared. Overriding this option here
163# so that the user need not explicitly set this (assuming
164# sharing sqc is the common usage)
165n_cu = options.num_compute_units
166num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc))
167options.num_sqc = num_sqc # pass this to Ruby
168
169########################## Creating the GPU system ########################
170# shader is the GPU
171shader = Shader(n_wf = options.wfs_per_simd,
172 clk_domain = SrcClockDomain(
173 clock = options.GPUClock,
174 voltage_domain = VoltageDomain(
175 voltage = options.gpu_voltage)),
176 timing = True)
177
178# GPU_RfO(Read For Ownership) implements SC/TSO memory model.
179# Other GPU protocols implement release consistency at GPU side.
180# So, all GPU protocols other than GPU_RfO should make their writes
181# visible to the global memory and should read from global memory
182# during kernal boundary. The pipeline initiates(or do not initiate)
183# the acquire/release operation depending on this impl_kern_boundary_sync
184# flag. This flag=true means pipeline initiates a acquire/release operation
185# at kernel boundary.
186if buildEnv['PROTOCOL'] == 'GPU_RfO':
187 shader.impl_kern_boundary_sync = False
188else:
189 shader.impl_kern_boundary_sync = True
190
191# Switching off per-lane TLB by default
192per_lane = False
193if options.TLB_config == "perLane":
194 per_lane = True
195
196# List of compute units; one GPU can have multiple compute units
197compute_units = []
198for i in xrange(n_cu):
199 compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
200 num_SIMDs = options.simds_per_cu,
201 wfSize = options.wf_size,
202 spbypass_pipe_length = \
203 options.sp_bypass_path_length,
204 dpbypass_pipe_length = \
205 options.dp_bypass_path_length,
206 issue_period = options.issue_period,
207 coalescer_to_vrf_bus_width = \
208 options.glbmem_rd_bus_width,
209 vrf_to_coalescer_bus_width = \
210 options.glbmem_wr_bus_width,
211 num_global_mem_pipes = \
212 options.glb_mem_pipes_per_cu,
213 num_shared_mem_pipes = \
214 options.shr_mem_pipes_per_cu,
215 n_wf = options.wfs_per_simd,
216 execPolicy = options.CUExecPolicy,
217 xactCasMode = options.xact_cas_mode,
218 debugSegFault = options.SegFaultDebug,
219 functionalTLB = True,
220 localMemBarrier = options.LocalMemBarrier,
221 countPages = options.countPages,
222 localDataStore = \
223 LdsState(banks = options.numLdsBanks,
224 bankConflictPenalty = \
225 options.ldsBankConflictPenalty)))
226 wavefronts = []
227 vrfs = []
228 for j in xrange(options.simds_per_cu):
229 for k in xrange(shader.n_wf):
230 wavefronts.append(Wavefront(simdId = j, wf_slot_id = k))
231 vrfs.append(VectorRegisterFile(simd_id=j,
232 num_regs_per_simd=options.vreg_file_size))
233 compute_units[-1].wavefronts = wavefronts
234 compute_units[-1].vector_register_file = vrfs
235 if options.TLB_prefetch:
236 compute_units[-1].prefetch_depth = options.TLB_prefetch
237 compute_units[-1].prefetch_prev_type = options.pf_type
238
239 # attach the LDS and the CU to the bus (actually a Bridge)
240 compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave
241 compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort
242
243# Attach compute units to GPU
244shader.CUs = compute_units
245
246# this is a uniprocessor only test, thus the shader is the second index in the
247# list of "system.cpus"
248options.num_cpus = 1
249shader_idx = 1
250cpu = TimingSimpleCPU(cpu_id=0)
251
252########################## Creating the GPU dispatcher ########################
253# Dispatcher dispatches work from host CPU to GPU
254host_cpu = cpu
255dispatcher = GpuDispatcher()
256
257# Currently does not test for command processors
258cpu_list = [cpu] + [shader] + [dispatcher]
259
260system = System(cpu = cpu_list,
261 mem_ranges = [AddrRange(options.mem_size)],
262 mem_mode = 'timing')
263
264# Dummy voltage domain for all our clock domains
265system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
266system.clk_domain = SrcClockDomain(clock = '1GHz',
267 voltage_domain = system.voltage_domain)
268
269# Create a seperate clock domain for components that should run at
270# CPUs frequency
271system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz',
272 voltage_domain = \
273 system.voltage_domain)
274
275# configure the TLB hierarchy
276GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx)
277
278# create Ruby system
279system.piobus = IOXBar(width=32, response_latency=0,
280 frontend_latency=0, forward_latency=0)
281Ruby.create_system(options, None, system)
282
283# Create a separate clock for Ruby
284system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
285 voltage_domain = system.voltage_domain)
286
287# create the interrupt controller
288cpu.createInterruptController()
289
290#
291# Tie the cpu cache ports to the ruby cpu ports and
292# physmem, respectively
293#
294cpu.connectAllPorts(system.ruby._cpu_ports[0])
295system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave
296
297# attach CU ports to Ruby
298# Because of the peculiarities of the CP core, you may have 1 CPU but 2
299# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be
300# hooked up until after the CP. To make this script generic, figure out
301# the index as below, but note that this assumes there is one sequencer
302# per compute unit and one sequencer per SQC for the math to work out
303# correctly.
304gpu_port_idx = len(system.ruby._cpu_ports) \
305 - options.num_compute_units - options.num_sqc
306gpu_port_idx = gpu_port_idx - options.num_cp * 2
307
308wavefront_size = options.wf_size
309for i in xrange(n_cu):
310 # The pipeline issues wavefront_size number of uncoalesced requests
311 # in one GPU issue cycle. Hence wavefront_size mem ports.
312 for j in xrange(wavefront_size):
313 system.cpu[shader_idx].CUs[i].memory_port[j] = \
314 system.ruby._cpu_ports[gpu_port_idx].slave[j]
315 gpu_port_idx += 1
316
317for i in xrange(n_cu):
318 if i > 0 and not i % options.cu_per_sqc:
319 gpu_port_idx += 1
320 system.cpu[shader_idx].CUs[i].sqc_port = \
321 system.ruby._cpu_ports[gpu_port_idx].slave
322gpu_port_idx = gpu_port_idx + 1
323
324# Current regression tests do not support the command processor
325assert(options.num_cp == 0)
326
327# connect dispatcher to the system.piobus
328dispatcher.pio = system.piobus.master
329dispatcher.dma = system.piobus.slave
330
331################# Connect the CPU and GPU via GPU Dispatcher ###################
332# CPU rings the GPU doorbell to notify a pending task
333# using this interface.
334# And GPU uses this interface to notify the CPU of task completion
335# The communcation happens through emulated driver.
336
337# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array
338# parameters must be after the explicit setting of the System cpu list
339shader.cpu_pointer = host_cpu
340dispatcher.cpu = host_cpu
341dispatcher.shader_pointer = shader
342
343# -----------------------
344# run simulation
345# -----------------------
346
347root = Root(full_system = False, system = system)
348m5.ticks.setGlobalFrequency('1THz')
349root.system.mem_mode = 'timing'
|