1#
2# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# For use for simulation and test purposes only
6#
7# Redistribution and use in source and binary forms, with or without
8# modification, are permitted provided that the following conditions are met:
9#
10# 1. Redistributions of source code must retain the above copyright notice,
11# this list of conditions and the following disclaimer.
12#
13# 2. Redistributions in binary form must reproduce the above copyright notice,
14# this list of conditions and the following disclaimer in the documentation
15# and/or other materials provided with the distribution.
16#
17# 3. Neither the name of the copyright holder nor the names of its contributors
18# may be used to endorse or promote products derived from this software
19# without specific prior written permission.
20#
21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31# POSSIBILITY OF SUCH DAMAGE.
32#
33# Author: Brad Beckmann
34#
35
36import m5
37from m5.objects import *
38from m5.defines import buildEnv
39from m5.util import addToPath
40import os, optparse, sys
41
| 1#
2# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# For use for simulation and test purposes only
6#
7# Redistribution and use in source and binary forms, with or without
8# modification, are permitted provided that the following conditions are met:
9#
10# 1. Redistributions of source code must retain the above copyright notice,
11# this list of conditions and the following disclaimer.
12#
13# 2. Redistributions in binary form must reproduce the above copyright notice,
14# this list of conditions and the following disclaimer in the documentation
15# and/or other materials provided with the distribution.
16#
17# 3. Neither the name of the copyright holder nor the names of its contributors
18# may be used to endorse or promote products derived from this software
19# without specific prior written permission.
20#
21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31# POSSIBILITY OF SUCH DAMAGE.
32#
33# Author: Brad Beckmann
34#
35
36import m5
37from m5.objects import *
38from m5.defines import buildEnv
39from m5.util import addToPath
40import os, optparse, sys
41
|
42m5.util.addToPath('../configs/common')
| |
43m5.util.addToPath('../configs/')
44
45from ruby import Ruby
| 42m5.util.addToPath('../configs/')
43
44from ruby import Ruby
|
46import Options
| 45from common import Options
|
47
48parser = optparse.OptionParser()
49Options.addCommonOptions(parser)
50
51# add the gpu specific options expected by the the gpu and gpu_RfO
52parser.add_option("-u", "--num-compute-units", type="int", default=8,
53 help="number of compute units in the GPU")
54parser.add_option("--num-cp", type="int", default=0,
55 help="Number of GPU Command Processors (CP)")
56parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
57 "per CU")
58parser.add_option("--wf-size", type="int", default=64,
59 help="Wavefront size(in workitems)")
60parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \
61 "WF slots per SIMD")
62
63# Add the ruby specific and protocol specific options
64Ruby.define_options(parser)
65
66(options, args) = parser.parse_args()
67
68#
69# Set the default cache size and associativity to be very small to encourage
70# races between requests and writebacks.
71#
72options.l1d_size="256B"
73options.l1i_size="256B"
74options.l2_size="512B"
75options.l3_size="1kB"
76options.l1d_assoc=2
77options.l1i_assoc=2
78options.l2_assoc=2
79options.l3_assoc=2
80options.num_compute_units=8
81options.num_sqc=2
82
83# Check to for the GPU_RfO protocol. Other GPU protocols are non-SC and will
84# not work with the Ruby random tester.
85assert(buildEnv['PROTOCOL'] == 'GPU_RfO')
86
87#
88# create the tester and system, including ruby
89#
90tester = RubyTester(check_flush = False, checks_to_complete = 100,
91 wakeup_frequency = 10, num_cpus = options.num_cpus)
92
93# We set the testers as cpu for ruby to find the correct clock domains
94# for the L1 Objects.
95system = System(cpu = tester)
96
97# Dummy voltage domain for all our clock domains
98system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
99system.clk_domain = SrcClockDomain(clock = '1GHz',
100 voltage_domain = system.voltage_domain)
101
102system.mem_ranges = AddrRange('256MB')
103
104Ruby.create_system(options, False, system)
105
106# Create a separate clock domain for Ruby
107system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
108 voltage_domain = system.voltage_domain)
109
110tester.num_cpus = len(system.ruby._cpu_ports)
111
112#
113# The tester is most effective when randomization is turned on and
114# artifical delay is randomly inserted on messages
115#
116system.ruby.randomization = True
117
118for ruby_port in system.ruby._cpu_ports:
119 #
120 # Tie the ruby tester ports to the ruby cpu read and write ports
121 #
122 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
123 tester.cpuInstDataPort = ruby_port.slave
124 elif ruby_port.support_data_reqs:
125 tester.cpuDataPort = ruby_port.slave
126 elif ruby_port.support_inst_reqs:
127 tester.cpuInstPort = ruby_port.slave
128
129 # Do not automatically retry stalled Ruby requests
130 ruby_port.no_retry_on_stall = True
131
132 #
133 # Tell the sequencer this is the ruby tester so that it
134 # copies the subblock back to the checker
135 #
136 ruby_port.using_ruby_tester = True
137
138# -----------------------
139# run simulation
140# -----------------------
141
142root = Root(full_system = False, system = system )
143root.system.mem_mode = 'timing'
144
145# Not much point in this being higher than the L1 latency
146m5.ticks.setGlobalFrequency('1ns')
| 46
47parser = optparse.OptionParser()
48Options.addCommonOptions(parser)
49
50# add the gpu specific options expected by the the gpu and gpu_RfO
51parser.add_option("-u", "--num-compute-units", type="int", default=8,
52 help="number of compute units in the GPU")
53parser.add_option("--num-cp", type="int", default=0,
54 help="Number of GPU Command Processors (CP)")
55parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
56 "per CU")
57parser.add_option("--wf-size", type="int", default=64,
58 help="Wavefront size(in workitems)")
59parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \
60 "WF slots per SIMD")
61
62# Add the ruby specific and protocol specific options
63Ruby.define_options(parser)
64
65(options, args) = parser.parse_args()
66
67#
68# Set the default cache size and associativity to be very small to encourage
69# races between requests and writebacks.
70#
71options.l1d_size="256B"
72options.l1i_size="256B"
73options.l2_size="512B"
74options.l3_size="1kB"
75options.l1d_assoc=2
76options.l1i_assoc=2
77options.l2_assoc=2
78options.l3_assoc=2
79options.num_compute_units=8
80options.num_sqc=2
81
82# Check to for the GPU_RfO protocol. Other GPU protocols are non-SC and will
83# not work with the Ruby random tester.
84assert(buildEnv['PROTOCOL'] == 'GPU_RfO')
85
86#
87# create the tester and system, including ruby
88#
89tester = RubyTester(check_flush = False, checks_to_complete = 100,
90 wakeup_frequency = 10, num_cpus = options.num_cpus)
91
92# We set the testers as cpu for ruby to find the correct clock domains
93# for the L1 Objects.
94system = System(cpu = tester)
95
96# Dummy voltage domain for all our clock domains
97system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
98system.clk_domain = SrcClockDomain(clock = '1GHz',
99 voltage_domain = system.voltage_domain)
100
101system.mem_ranges = AddrRange('256MB')
102
103Ruby.create_system(options, False, system)
104
105# Create a separate clock domain for Ruby
106system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
107 voltage_domain = system.voltage_domain)
108
109tester.num_cpus = len(system.ruby._cpu_ports)
110
111#
112# The tester is most effective when randomization is turned on and
113# artifical delay is randomly inserted on messages
114#
115system.ruby.randomization = True
116
117for ruby_port in system.ruby._cpu_ports:
118 #
119 # Tie the ruby tester ports to the ruby cpu read and write ports
120 #
121 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
122 tester.cpuInstDataPort = ruby_port.slave
123 elif ruby_port.support_data_reqs:
124 tester.cpuDataPort = ruby_port.slave
125 elif ruby_port.support_inst_reqs:
126 tester.cpuInstPort = ruby_port.slave
127
128 # Do not automatically retry stalled Ruby requests
129 ruby_port.no_retry_on_stall = True
130
131 #
132 # Tell the sequencer this is the ruby tester so that it
133 # copies the subblock back to the checker
134 #
135 ruby_port.using_ruby_tester = True
136
137# -----------------------
138# run simulation
139# -----------------------
140
141root = Root(full_system = False, system = system )
142root.system.mem_mode = 'timing'
143
144# Not much point in this being higher than the L1 latency
145m5.ticks.setGlobalFrequency('1ns')
|