| base_config.py (9835:cc7a7fc71c42) | base_config.py (10405:7a618c07e663) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 88 unchanged lines hidden (view full) --- 97 """Add shared caches to a system. 98 99 Arguments: 100 system -- System to work on. 101 102 Returns: 103 A bus that CPUs should use to connect to the shared cache. 104 """ | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 88 unchanged lines hidden (view full) --- 97 """Add shared caches to a system. 98 99 Arguments: 100 system -- System to work on. 101 102 Returns: 103 A bus that CPUs should use to connect to the shared cache. 104 """ |
| 105 system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain) | 105 system.toL2Bus = CoherentXBar(clk_domain=system.cpu_clk_domain) |
| 106 system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 107 size='4MB', assoc=8) 108 system.l2c.cpu_side = system.toL2Bus.master 109 system.l2c.mem_side = system.membus.slave 110 return system.toL2Bus 111 112 def init_cpu(self, system, cpu, sha_bus): 113 """Initialize a CPU. --- 65 unchanged lines hidden (view full) --- 179 def __init__(self, **kwargs): 180 BaseSystem.__init__(self, **kwargs) 181 182 def init_system(self, system): 183 BaseSystem.init_system(self, system) 184 185 def create_system(self): 186 system = System(physmem = self.mem_class(), | 106 system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 107 size='4MB', assoc=8) 108 system.l2c.cpu_side = system.toL2Bus.master 109 system.l2c.mem_side = system.membus.slave 110 return system.toL2Bus 111 112 def init_cpu(self, system, cpu, sha_bus): 113 """Initialize a CPU. --- 65 unchanged lines hidden (view full) --- 179 def __init__(self, **kwargs): 180 BaseSystem.__init__(self, **kwargs) 181 182 def init_system(self, system): 183 BaseSystem.init_system(self, system) 184 185 def create_system(self): 186 system = System(physmem = self.mem_class(), |
| 187 membus = CoherentBus(), | 187 membus = CoherentXBar(), |
| 188 mem_mode = self.mem_mode) 189 system.system_port = system.membus.slave 190 system.physmem.port = system.membus.master 191 self.init_system(system) 192 return system 193 194 def create_root(self): 195 system = self.create_system() --- 82 unchanged lines hidden --- | 188 mem_mode = self.mem_mode) 189 system.system_port = system.membus.slave 190 system.physmem.port = system.membus.master 191 self.init_system(system) 192 return system 193 194 def create_root(self): 195 system = self.create_system() --- 82 unchanged lines hidden --- |