| base_config.py (9827:f47274776aa0) | base_config.py (9835:cc7a7fc71c42) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 214 unchanged lines hidden (view full) --- 223 def __init__(self, **kwargs): 224 BaseSystem.__init__(self, **kwargs) 225 226 def init_system(self, system): 227 BaseSystem.init_system(self, system) 228 229 # create the memory controllers and connect them, stick with 230 # the physmem name to avoid bumping all the reference stats | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 214 unchanged lines hidden (view full) --- 223 def __init__(self, **kwargs): 224 BaseSystem.__init__(self, **kwargs) 225 226 def init_system(self, system): 227 BaseSystem.init_system(self, system) 228 229 # create the memory controllers and connect them, stick with 230 # the physmem name to avoid bumping all the reference stats |
| 231 system.physmem = [self.mem_class(range = r, 232 conf_table_reported = True) | 231 system.physmem = [self.mem_class(range = r) |
| 233 for r in system.mem_ranges] 234 for i in xrange(len(system.physmem)): 235 system.physmem[i].port = system.membus.master 236 237 # create the iocache, which by default runs at the system clock 238 system.iocache = IOCache(addr_ranges=system.mem_ranges) 239 system.iocache.cpu_side = system.iobus.master 240 system.iocache.mem_side = system.membus.slave --- 38 unchanged lines hidden --- | 232 for r in system.mem_ranges] 233 for i in xrange(len(system.physmem)): 234 system.physmem[i].port = system.membus.master 235 236 # create the iocache, which by default runs at the system clock 237 system.iocache = IOCache(addr_ranges=system.mem_ranges) 238 system.iocache.cpu_side = system.iobus.master 239 system.iocache.mem_side = system.membus.slave --- 38 unchanged lines hidden --- |