| base_config.py (9793:6e6cefc1db1f) | base_config.py (9826:014ff1fbff6d) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 207 unchanged lines hidden (view full) --- 216 """Basic full system builder.""" 217 218 def __init__(self, **kwargs): 219 BaseSystem.__init__(self, **kwargs) 220 221 def init_system(self, system): 222 BaseSystem.init_system(self, system) 223 | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 207 unchanged lines hidden (view full) --- 216 """Basic full system builder.""" 217 218 def __init__(self, **kwargs): 219 BaseSystem.__init__(self, **kwargs) 220 221 def init_system(self, system): 222 BaseSystem.init_system(self, system) 223 |
| 224 # create the memory controllers and connect them, stick with 225 # the physmem name to avoid bumping all the reference stats 226 system.physmem = [self.mem_class(range = r, 227 conf_table_reported = True) 228 for r in system.mem_ranges] 229 for i in xrange(len(system.physmem)): 230 system.physmem[i].port = system.membus.master 231 |
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| 224 # create the iocache, which by default runs at the system clock 225 system.iocache = IOCache(addr_ranges=system.mem_ranges) 226 system.iocache.cpu_side = system.iobus.master 227 system.iocache.mem_side = system.membus.slave 228 229 def create_root(self): 230 system = self.create_system() 231 m5.ticks.setGlobalFrequency('1THz') --- 34 unchanged lines hidden --- | 232 # create the iocache, which by default runs at the system clock 233 system.iocache = IOCache(addr_ranges=system.mem_ranges) 234 system.iocache.cpu_side = system.iobus.master 235 system.iocache.mem_side = system.membus.slave 236 237 def create_root(self): 238 system = self.create_system() 239 m5.ticks.setGlobalFrequency('1THz') --- 34 unchanged lines hidden --- |