| base_config.py (9790:ccc428657233) | base_config.py (9792:c02004c2cc5b) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited | 1# Copyright (c) 2012-2013 ARM Limited |
| 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 19 unchanged lines hidden (view full) --- 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 19 unchanged lines hidden (view full) --- 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg |
| 37# Andreas Hansson |
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| 37 38from abc import ABCMeta, abstractmethod 39import m5 40from m5.objects import * 41from m5.proxy import * 42m5.util.addToPath('../configs/common') 43import FSConfig 44from Caches import * --- 6 unchanged lines hidden (view full) --- 51 This class provides some basic functionality for creating an ARM 52 system with the usual peripherals (caches, GIC, etc.). It allows 53 customization by defining separate methods for different parts of 54 the initialization process. 55 """ 56 57 __metaclass__ = ABCMeta 58 | 38 39from abc import ABCMeta, abstractmethod 40import m5 41from m5.objects import * 42from m5.proxy import * 43m5.util.addToPath('../configs/common') 44import FSConfig 45from Caches import * --- 6 unchanged lines hidden (view full) --- 52 This class provides some basic functionality for creating an ARM 53 system with the usual peripherals (caches, GIC, etc.). It allows 54 customization by defining separate methods for different parts of 55 the initialization process. 56 """ 57 58 __metaclass__ = ABCMeta 59 |
| 59 def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU, 60 num_cpus=1, checker=False): 61 """Initialize a simple ARM system. | 60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory, 61 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False): 62 """Initialize a simple base system. |
| 62 63 Keyword Arguments: 64 mem_mode -- String describing the memory mode (timing or atomic) | 63 64 Keyword Arguments: 65 mem_mode -- String describing the memory mode (timing or atomic) |
| 66 mem_class -- Memory controller class to use |
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| 65 cpu_class -- CPU class to use 66 num_cpus -- Number of CPUs to instantiate 67 checker -- Set to True to add checker CPUs 68 """ 69 self.mem_mode = mem_mode | 67 cpu_class -- CPU class to use 68 num_cpus -- Number of CPUs to instantiate 69 checker -- Set to True to add checker CPUs 70 """ 71 self.mem_mode = mem_mode |
| 72 self.mem_class = mem_class |
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| 70 self.cpu_class = cpu_class 71 self.num_cpus = num_cpus 72 self.checker = checker 73 74 def create_cpus(self): 75 """Return a list of CPU objects to add to a system.""" 76 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') 77 for i in range(self.num_cpus) ] --- 70 unchanged lines hidden (view full) --- 148 pass 149 150 @abstractmethod 151 def create_root(self): 152 """Create and return a simulation root using the system 153 defined by this class.""" 154 pass 155 | 73 self.cpu_class = cpu_class 74 self.num_cpus = num_cpus 75 self.checker = checker 76 77 def create_cpus(self): 78 """Return a list of CPU objects to add to a system.""" 79 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') 80 for i in range(self.num_cpus) ] --- 70 unchanged lines hidden (view full) --- 151 pass 152 153 @abstractmethod 154 def create_root(self): 155 """Create and return a simulation root using the system 156 defined by this class.""" 157 pass 158 |
| 159class BaseSESystem(BaseSystem): 160 """Basic syscall-emulation builder.""" 161 162 def __init__(self, **kwargs): 163 BaseSystem.__init__(self, **kwargs) 164 165 def init_system(self, system): 166 BaseSystem.init_system(self, system) 167 168 def create_system(self): 169 system = System(physmem = self.mem_class(), 170 membus = CoherentBus(), 171 mem_mode = self.mem_mode) 172 system.system_port = system.membus.slave 173 system.physmem.port = system.membus.master 174 self.init_system(system) 175 return system 176 177 def create_root(self): 178 system = self.create_system() 179 m5.ticks.setGlobalFrequency('1THz') 180 return Root(full_system=False, system=system) 181 182class BaseSESystemUniprocessor(BaseSESystem): 183 """Basic syscall-emulation builder for uniprocessor systems. 184 185 Note: This class is only really needed to provide backwards 186 compatibility in existing test cases. 187 """ 188 189 def __init__(self, **kwargs): 190 BaseSESystem.__init__(self, **kwargs) 191 192 def create_caches_private(self, cpu): 193 # The atomic SE configurations do not use caches 194 if self.mem_mode == "timing": 195 # @todo We might want to revisit these rather enthusiastic L1 sizes 196 cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'), 197 L1Cache(size='256kB'), 198 L2Cache(size='2MB')) 199 200 def create_caches_shared(self, system): 201 return None 202 |
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| 156class BaseFSSystem(BaseSystem): 157 """Basic full system builder.""" 158 159 def __init__(self, **kwargs): 160 BaseSystem.__init__(self, **kwargs) 161 162 def init_system(self, system): 163 BaseSystem.init_system(self, system) --- 41 unchanged lines hidden --- | 203class BaseFSSystem(BaseSystem): 204 """Basic full system builder.""" 205 206 def __init__(self, **kwargs): 207 BaseSystem.__init__(self, **kwargs) 208 209 def init_system(self, system): 210 BaseSystem.init_system(self, system) --- 41 unchanged lines hidden --- |