base_config.py (9654:64b653b3d72f) base_config.py (9674:d35bd171cf2a)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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99 A bus that CPUs should use to connect to the shared cache.
100 """
101 system.toL2Bus = CoherentBus(clock='2GHz')
102 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
103 system.l2c.cpu_side = system.toL2Bus.master
104 system.l2c.mem_side = system.membus.slave
105 return system.toL2Bus
106
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 90 unchanged lines hidden (view full) ---

99 A bus that CPUs should use to connect to the shared cache.
100 """
101 system.toL2Bus = CoherentBus(clock='2GHz')
102 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
103 system.l2c.cpu_side = system.toL2Bus.master
104 system.l2c.mem_side = system.membus.slave
105 return system.toL2Bus
106
107 def init_cpu(self, system, cpu):
107 def init_cpu(self, system, cpu, sha_bus):
108 """Initialize a CPU.
109
110 Arguments:
111 system -- System to work on.
112 cpu -- CPU to initialize.
113 """
108 """Initialize a CPU.
109
110 Arguments:
111 system -- System to work on.
112 cpu -- CPU to initialize.
113 """
114 cpu.createInterruptController()
114 if not cpu.switched_out:
115 self.create_caches_private(cpu)
116 cpu.createInterruptController()
117 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
118 system.membus)
115
116 def init_kvm(self, system):
117 """Do KVM-specific system initialization.
118
119 Arguments:
120 system -- System to work on.
121 """
122 system.vm = KvmVM()

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130 system.cpu = self.create_cpus()
131
132 if _have_kvm_support and \
133 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
134 self.init_kvm(system)
135
136 sha_bus = self.create_caches_shared(system)
137 for cpu in system.cpu:
119
120 def init_kvm(self, system):
121 """Do KVM-specific system initialization.
122
123 Arguments:
124 system -- System to work on.
125 """
126 system.vm = KvmVM()

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134 system.cpu = self.create_cpus()
135
136 if _have_kvm_support and \
137 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
138 self.init_kvm(system)
139
140 sha_bus = self.create_caches_shared(system)
141 for cpu in system.cpu:
138 if not cpu.switched_out:
139 self.create_caches_private(cpu)
140 self.init_cpu(system, cpu)
141 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
142 system.membus)
143 else:
144 self.init_cpu(system, cpu)
142 self.init_cpu(system, cpu, sha_bus)
145
146 @abstractmethod
147 def create_system(self):
148 """Create an return an initialized system."""
149 pass
150
151 @abstractmethod
152 def create_root(self):

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144 @abstractmethod
145 def create_system(self):
146 """Create an return an initialized system."""
147 pass
148
149 @abstractmethod
150 def create_root(self):

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