| base_config.py (12726:850e9965525b) | base_config.py (13718:89e8bcc7253b) |
|---|---|
| 1# Copyright (c) 2012-2013, 2017-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 274 unchanged lines hidden (view full) --- 283 assoc = 2, 284 mshrs = 128, 285 tag_latency = 10, 286 data_latency = 10, 287 sequential_access = True, 288 response_latency = 20, 289 tgts_per_mshr = 8) 290 for r in system.mem_ranges] | 1# Copyright (c) 2012-2013, 2017-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 274 unchanged lines hidden (view full) --- 283 assoc = 2, 284 mshrs = 128, 285 tag_latency = 10, 286 data_latency = 10, 287 sequential_access = True, 288 response_latency = 20, 289 tgts_per_mshr = 8) 290 for r in system.mem_ranges] |
| 291 for i in xrange(len(system.physmem)): | 291 for i in range(len(system.physmem)): |
| 292 system.physmem[i].port = system.llc[i].mem_side 293 system.llc[i].cpu_side = system.membus.master 294 295 # create the iocache, which by default runs at the system clock 296 system.iocache = IOCache(addr_ranges=system.mem_ranges) 297 system.iocache.cpu_side = system.iobus.master 298 system.iocache.mem_side = system.membus.slave 299 --- 37 unchanged lines hidden --- | 292 system.physmem[i].port = system.llc[i].mem_side 293 system.llc[i].cpu_side = system.membus.master 294 295 # create the iocache, which by default runs at the system clock 296 system.iocache = IOCache(addr_ranges=system.mem_ranges) 297 system.iocache.cpu_side = system.iobus.master 298 system.iocache.mem_side = system.membus.slave 299 --- 37 unchanged lines hidden --- |