base_config.py (11682:612f75cf36a0) base_config.py (12070:d89ac2ebc159)
1# Copyright (c) 2012-2013 ARM Limited
1# Copyright (c) 2012-2013, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39from abc import ABCMeta, abstractmethod
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39from abc import ABCMeta, abstractmethod
40import optparse
40import m5
41from m5.objects import *
42from m5.proxy import *
43m5.util.addToPath('../configs/')
44from common import FSConfig
41import m5
42from m5.objects import *
43from m5.proxy import *
44m5.util.addToPath('../configs/')
45from common import FSConfig
46from common import Options
45from common.Caches import *
47from common.Caches import *
48from ruby import Ruby
46
47_have_kvm_support = 'BaseKvmCPU' in globals()
48
49class BaseSystem(object):
50 """Base system builder.
51
52 This class provides some basic functionality for creating an ARM
53 system with the usual peripherals (caches, GIC, etc.). It allows
54 customization by defining separate methods for different parts of
55 the initialization process.
56 """
57
58 __metaclass__ = ABCMeta
59
60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
61 cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
49
50_have_kvm_support = 'BaseKvmCPU' in globals()
51
52class BaseSystem(object):
53 """Base system builder.
54
55 This class provides some basic functionality for creating an ARM
56 system with the usual peripherals (caches, GIC, etc.). It allows
57 customization by defining separate methods for different parts of
58 the initialization process.
59 """
60
61 __metaclass__ = ABCMeta
62
63 def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
64 cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
62 checker=False,
63 mem_size=None):
65 checker=False, mem_size=None, use_ruby=False):
64 """Initialize a simple base system.
65
66 Keyword Arguments:
67 mem_mode -- String describing the memory mode (timing or atomic)
68 mem_class -- Memory controller class to use
69 cpu_class -- CPU class to use
70 num_cpus -- Number of CPUs to instantiate
71 checker -- Set to True to add checker CPUs
72 mem_size -- Override the default memory size
66 """Initialize a simple base system.
67
68 Keyword Arguments:
69 mem_mode -- String describing the memory mode (timing or atomic)
70 mem_class -- Memory controller class to use
71 cpu_class -- CPU class to use
72 num_cpus -- Number of CPUs to instantiate
73 checker -- Set to True to add checker CPUs
74 mem_size -- Override the default memory size
75 use_ruby -- Set to True to use ruby memory
73 """
74 self.mem_mode = mem_mode
75 self.mem_class = mem_class
76 self.cpu_class = cpu_class
77 self.num_cpus = num_cpus
78 self.num_threads = num_threads
79 self.checker = checker
76 """
77 self.mem_mode = mem_mode
78 self.mem_class = mem_class
79 self.cpu_class = cpu_class
80 self.num_cpus = num_cpus
81 self.num_threads = num_threads
82 self.checker = checker
83 self.use_ruby = use_ruby
80
81 def create_cpus(self, cpu_clk_domain):
82 """Return a list of CPU objects to add to a system."""
83 cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
84 numThreads=self.num_threads,
85 cpu_id=i)
86 for i in range(self.num_cpus) ]
87 if self.checker:

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143 """
144 self.create_clk_src(system)
145 system.cpu = self.create_cpus(system.cpu_clk_domain)
146
147 if _have_kvm_support and \
148 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
149 self.init_kvm(system)
150
84
85 def create_cpus(self, cpu_clk_domain):
86 """Return a list of CPU objects to add to a system."""
87 cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
88 numThreads=self.num_threads,
89 cpu_id=i)
90 for i in range(self.num_cpus) ]
91 if self.checker:

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147 """
148 self.create_clk_src(system)
149 system.cpu = self.create_cpus(system.cpu_clk_domain)
150
151 if _have_kvm_support and \
152 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
153 self.init_kvm(system)
154
151 sha_bus = self.create_caches_shared(system)
155 if self.use_ruby:
156 # Add the ruby specific and protocol specific options
157 parser = optparse.OptionParser()
158 Options.addCommonOptions(parser)
159 Ruby.define_options(parser)
160 (options, args) = parser.parse_args()
152
161
153 for cpu in system.cpu:
154 self.init_cpu(system, cpu, sha_bus)
162 # Set the default cache size and associativity to be very
163 # small to encourage races between requests and writebacks.
164 options.l1d_size="32kB"
165 options.l1i_size="32kB"
166 options.l2_size="4MB"
167 options.l1d_assoc=4
168 options.l1i_assoc=2
169 options.l2_assoc=8
170 options.num_cpus = self.num_cpus
171 options.num_dirs = 2
155
172
173 Ruby.create_system(options, True, system, system.iobus,
174 system._dma_ports)
175
176 # Create a seperate clock domain for Ruby
177 system.ruby.clk_domain = SrcClockDomain(
178 clock = options.ruby_clock,
179 voltage_domain = system.voltage_domain)
180 for i, cpu in enumerate(system.cpu):
181 if not cpu.switched_out:
182 cpu.createInterruptController()
183 cpu.connectCachedPorts(system.ruby._cpu_ports[i])
184 else:
185 sha_bus = self.create_caches_shared(system)
186 for cpu in system.cpu:
187 self.init_cpu(system, cpu, sha_bus)
188
189
156 def create_clk_src(self,system):
157 # Create system clock domain. This provides clock value to every
158 # clocked object that lies beneath it unless explicitly overwritten
159 # by a different clock domain.
160 system.voltage_domain = VoltageDomain()
161 system.clk_domain = SrcClockDomain(clock = '1GHz',
162 voltage_domain =
163 system.voltage_domain)

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188 def init_system(self, system):
189 BaseSystem.init_system(self, system)
190
191 def create_system(self):
192 system = System(physmem = self.mem_class(),
193 membus = SystemXBar(),
194 mem_mode = self.mem_mode,
195 multi_thread = (self.num_threads > 1))
190 def create_clk_src(self,system):
191 # Create system clock domain. This provides clock value to every
192 # clocked object that lies beneath it unless explicitly overwritten
193 # by a different clock domain.
194 system.voltage_domain = VoltageDomain()
195 system.clk_domain = SrcClockDomain(clock = '1GHz',
196 voltage_domain =
197 system.voltage_domain)

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222 def init_system(self, system):
223 BaseSystem.init_system(self, system)
224
225 def create_system(self):
226 system = System(physmem = self.mem_class(),
227 membus = SystemXBar(),
228 mem_mode = self.mem_mode,
229 multi_thread = (self.num_threads > 1))
196 system.system_port = system.membus.slave
230 if not self.use_ruby:
231 system.system_port = system.membus.slave
197 system.physmem.port = system.membus.master
198 self.init_system(system)
199 return system
200
201 def create_root(self):
202 system = self.create_system()
203 m5.ticks.setGlobalFrequency('1THz')
204 return Root(full_system=False, system=system)

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228 """Basic full system builder."""
229
230 def __init__(self, **kwargs):
231 BaseSystem.__init__(self, **kwargs)
232
233 def init_system(self, system):
234 BaseSystem.init_system(self, system)
235
232 system.physmem.port = system.membus.master
233 self.init_system(system)
234 return system
235
236 def create_root(self):
237 system = self.create_system()
238 m5.ticks.setGlobalFrequency('1THz')
239 return Root(full_system=False, system=system)

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263 """Basic full system builder."""
264
265 def __init__(self, **kwargs):
266 BaseSystem.__init__(self, **kwargs)
267
268 def init_system(self, system):
269 BaseSystem.init_system(self, system)
270
236 # create the memory controllers and connect them, stick with
237 # the physmem name to avoid bumping all the reference stats
238 system.physmem = [self.mem_class(range = r)
239 for r in system.mem_ranges]
240 for i in xrange(len(system.physmem)):
241 system.physmem[i].port = system.membus.master
271 if self.use_ruby:
272 # Connect the ruby io port to the PIO bus,
273 # assuming that there is just one such port.
274 system.iobus.master = system.ruby._io_port.slave
275 else:
276 # create the memory controllers and connect them, stick with
277 # the physmem name to avoid bumping all the reference stats
278 system.physmem = [self.mem_class(range = r)
279 for r in system.mem_ranges]
280 for i in xrange(len(system.physmem)):
281 system.physmem[i].port = system.membus.master
242
282
243 # create the iocache, which by default runs at the system clock
244 system.iocache = IOCache(addr_ranges=system.mem_ranges)
245 system.iocache.cpu_side = system.iobus.master
246 system.iocache.mem_side = system.membus.slave
283 # create the iocache, which by default runs at the system clock
284 system.iocache = IOCache(addr_ranges=system.mem_ranges)
285 system.iocache.cpu_side = system.iobus.master
286 system.iocache.mem_side = system.membus.slave
247
248 def create_root(self):
249 system = self.create_system()
250 m5.ticks.setGlobalFrequency('1THz')
251 return Root(full_system=True, system=system)
252
253class BaseFSSystemUniprocessor(BaseFSSystem):
254 """Basic full system builder for uniprocessor systems.

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288 def create_root(self):
289 system = self.create_system()
290 m5.ticks.setGlobalFrequency('1THz')
291 return Root(full_system=True, system=system)
292
293class BaseFSSystemUniprocessor(BaseFSSystem):
294 """Basic full system builder for uniprocessor systems.

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