base_config.py (10884:c60acdbdd6ad) base_config.py (11156:a37dda0f0202)
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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53 system with the usual peripherals (caches, GIC, etc.). It allows
54 customization by defining separate methods for different parts of
55 the initialization process.
56 """
57
58 __metaclass__ = ABCMeta
59
60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 44 unchanged lines hidden (view full) ---

53 system with the usual peripherals (caches, GIC, etc.). It allows
54 customization by defining separate methods for different parts of
55 the initialization process.
56 """
57
58 __metaclass__ = ABCMeta
59
60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
61 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False,
61 cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
62 checker=False,
62 mem_size=None):
63 """Initialize a simple base system.
64
65 Keyword Arguments:
66 mem_mode -- String describing the memory mode (timing or atomic)
67 mem_class -- Memory controller class to use
68 cpu_class -- CPU class to use
69 num_cpus -- Number of CPUs to instantiate
70 checker -- Set to True to add checker CPUs
71 mem_size -- Override the default memory size
72 """
73 self.mem_mode = mem_mode
74 self.mem_class = mem_class
75 self.cpu_class = cpu_class
76 self.num_cpus = num_cpus
63 mem_size=None):
64 """Initialize a simple base system.
65
66 Keyword Arguments:
67 mem_mode -- String describing the memory mode (timing or atomic)
68 mem_class -- Memory controller class to use
69 cpu_class -- CPU class to use
70 num_cpus -- Number of CPUs to instantiate
71 checker -- Set to True to add checker CPUs
72 mem_size -- Override the default memory size
73 """
74 self.mem_mode = mem_mode
75 self.mem_class = mem_class
76 self.cpu_class = cpu_class
77 self.num_cpus = num_cpus
78 self.num_threads = num_threads
77 self.checker = checker
78
79 def create_cpus(self, cpu_clk_domain):
80 """Return a list of CPU objects to add to a system."""
79 self.checker = checker
80
81 def create_cpus(self, cpu_clk_domain):
82 """Return a list of CPU objects to add to a system."""
81 cpus = [ self.cpu_class(clk_domain = cpu_clk_domain,
83 cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
84 numThreads=self.num_threads,
82 cpu_id=i)
83 for i in range(self.num_cpus) ]
84 if self.checker:
85 for c in cpus:
86 c.addCheckerCpu()
87 return cpus
88
89 def create_caches_private(self, cpu):

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182 BaseSystem.__init__(self, **kwargs)
183
184 def init_system(self, system):
185 BaseSystem.init_system(self, system)
186
187 def create_system(self):
188 system = System(physmem = self.mem_class(),
189 membus = SystemXBar(),
85 cpu_id=i)
86 for i in range(self.num_cpus) ]
87 if self.checker:
88 for c in cpus:
89 c.addCheckerCpu()
90 return cpus
91
92 def create_caches_private(self, cpu):

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185 BaseSystem.__init__(self, **kwargs)
186
187 def init_system(self, system):
188 BaseSystem.init_system(self, system)
189
190 def create_system(self):
191 system = System(physmem = self.mem_class(),
192 membus = SystemXBar(),
190 mem_mode = self.mem_mode)
193 mem_mode = self.mem_mode,
194 multi_thread = (self.num_threads > 1))
191 system.system_port = system.membus.slave
192 system.physmem.port = system.membus.master
193 self.init_system(system)
194 return system
195
196 def create_root(self):
197 system = self.create_system()
198 m5.ticks.setGlobalFrequency('1THz')

--- 81 unchanged lines hidden --- 		195 system.system_port = system.membus.slave
196 system.physmem.port = system.membus.master
197 self.init_system(system)
198 return system
199
200 def create_root(self):
201 system = self.create_system()
202 m5.ticks.setGlobalFrequency('1THz')

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