| base_config.py (10512:b423e1d0735e) | base_config.py (10720:67b3e74de9ae) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 90 unchanged lines hidden (view full) --- 99 """Add shared caches to a system. 100 101 Arguments: 102 system -- System to work on. 103 104 Returns: 105 A bus that CPUs should use to connect to the shared cache. 106 """ | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 90 unchanged lines hidden (view full) --- 99 """Add shared caches to a system. 100 101 Arguments: 102 system -- System to work on. 103 104 Returns: 105 A bus that CPUs should use to connect to the shared cache. 106 """ |
| 107 system.toL2Bus = CoherentXBar(clk_domain=system.cpu_clk_domain) | 107 system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain) |
| 108 system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 109 size='4MB', assoc=8) 110 system.l2c.cpu_side = system.toL2Bus.master 111 system.l2c.mem_side = system.membus.slave 112 return system.toL2Bus 113 114 def init_cpu(self, system, cpu, sha_bus): 115 """Initialize a CPU. --- 65 unchanged lines hidden (view full) --- 181 def __init__(self, **kwargs): 182 BaseSystem.__init__(self, **kwargs) 183 184 def init_system(self, system): 185 BaseSystem.init_system(self, system) 186 187 def create_system(self): 188 system = System(physmem = self.mem_class(), | 108 system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 109 size='4MB', assoc=8) 110 system.l2c.cpu_side = system.toL2Bus.master 111 system.l2c.mem_side = system.membus.slave 112 return system.toL2Bus 113 114 def init_cpu(self, system, cpu, sha_bus): 115 """Initialize a CPU. --- 65 unchanged lines hidden (view full) --- 181 def __init__(self, **kwargs): 182 BaseSystem.__init__(self, **kwargs) 183 184 def init_system(self, system): 185 BaseSystem.init_system(self, system) 186 187 def create_system(self): 188 system = System(physmem = self.mem_class(), |
| 189 membus = CoherentXBar(), | 189 membus = SystemXBar(), |
| 190 mem_mode = self.mem_mode) 191 system.system_port = system.membus.slave 192 system.physmem.port = system.membus.master 193 self.init_system(system) 194 return system 195 196 def create_root(self): 197 system = self.create_system() --- 82 unchanged lines hidden --- | 190 mem_mode = self.mem_mode) 191 system.system_port = system.membus.slave 192 system.physmem.port = system.membus.master 193 self.init_system(system) 194 return system 195 196 def create_root(self): 197 system = self.create_system() --- 82 unchanged lines hidden --- |