1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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69 checker -- Set to True to add checker CPUs
70 """
71 self.mem_mode = mem_mode
72 self.mem_class = mem_class
73 self.cpu_class = cpu_class
74 self.num_cpus = num_cpus
75 self.checker = checker
76
77 def create_cpus(self):
77 def create_cpus(self, cpu_clk_domain):
78 """Return a list of CPU objects to add to a system."""
79 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
79 cpus = [ self.cpu_class(clk_domain = cpu_clk_domain,
80 cpu_id=i)
81 for i in range(self.num_cpus) ]
82 if self.checker:
83 for c in cpus:
84 c.addCheckerCpu()
85 return cpus
86
87 def create_caches_private(self, cpu):
88 """Add private caches to a CPU.

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97 """Add shared caches to a system.
98
99 Arguments:
100 system -- System to work on.
101
102 Returns:
103 A bus that CPUs should use to connect to the shared cache.
104 """
104 system.toL2Bus = CoherentBus(clock='2GHz')
105 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
105 system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain)
106 system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
107 size='4MB', assoc=8)
108 system.l2c.cpu_side = system.toL2Bus.master
109 system.l2c.mem_side = system.membus.slave
110 return system.toL2Bus
111
112 def init_cpu(self, system, cpu, sha_bus):
113 """Initialize a CPU.
114
115 Arguments:

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131 system.vm = KvmVM()
132
133 def init_system(self, system):
134 """Initialize a system.
135
136 Arguments:
137 system -- System to initialize.
138 """
137 system.clock = '1GHz'
138 system.cpu = self.create_cpus()
139 self.create_clk_src(system)
140 system.cpu = self.create_cpus(system.cpu_clk_domain)
141
142 if _have_kvm_support and \
143 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
144 self.init_kvm(system)
145
146 sha_bus = self.create_caches_shared(system)
147 for cpu in system.cpu:
148 self.init_cpu(system, cpu, sha_bus)
149
150 def create_clk_src(self,system):
151 # Create system clock domain. This provides clock value to every
152 # clocked object that lies beneath it unless explicitly overwritten
153 # by a different clock domain.
154 system.clk_domain = SrcClockDomain(clock = '1GHz')
155
156 # Create a seperate clock domain for components that should
157 # run at CPUs frequency
158 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
159
160 @abstractmethod
161 def create_system(self):
162 """Create an return an initialized system."""
163 pass
164
165 @abstractmethod
166 def create_root(self):
167 """Create and return a simulation root using the system

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251
252class BaseFSSwitcheroo(BaseFSSystem):
253 """Uniprocessor system prepared for CPU switching"""
254
255 def __init__(self, cpu_classes, **kwargs):
256 BaseFSSystem.__init__(self, **kwargs)
257 self.cpu_classes = tuple(cpu_classes)
258
247 def create_cpus(self):
248 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
259 def create_cpus(self, cpu_clk_domain):
260 cpus = [ cclass(clk_domain = cpu_clk_domain,
261 cpu_id=0,
262 switched_out=True)
263 for cclass in self.cpu_classes ]
264 cpus[0].switched_out = False
265 return cpus