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> # create the memory controllers and connect them, stick with
> # the physmem name to avoid bumping all the reference stats
> system.physmem = [self.mem_class(range = r,
> conf_table_reported = True)
> for r in system.mem_ranges]
> for i in xrange(len(system.physmem)):
> system.physmem[i].port = system.membus.master
>