1# Copyright (c) 2012 ARM Limited
| 1# Copyright (c) 2012-2013 ARM Limited
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2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg
| 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg
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| 37# Andreas Hansson
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37 38from abc import ABCMeta, abstractmethod 39import m5 40from m5.objects import * 41from m5.proxy import * 42m5.util.addToPath('../configs/common') 43import FSConfig 44from Caches import * 45 46_have_kvm_support = 'BaseKvmCPU' in globals() 47 48class BaseSystem(object): 49 """Base system builder. 50 51 This class provides some basic functionality for creating an ARM 52 system with the usual peripherals (caches, GIC, etc.). It allows 53 customization by defining separate methods for different parts of 54 the initialization process. 55 """ 56 57 __metaclass__ = ABCMeta 58
| 38 39from abc import ABCMeta, abstractmethod 40import m5 41from m5.objects import * 42from m5.proxy import * 43m5.util.addToPath('../configs/common') 44import FSConfig 45from Caches import * 46 47_have_kvm_support = 'BaseKvmCPU' in globals() 48 49class BaseSystem(object): 50 """Base system builder. 51 52 This class provides some basic functionality for creating an ARM 53 system with the usual peripherals (caches, GIC, etc.). It allows 54 customization by defining separate methods for different parts of 55 the initialization process. 56 """ 57 58 __metaclass__ = ABCMeta 59
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59 def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU, 60 num_cpus=1, checker=False): 61 """Initialize a simple ARM system.
| 60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory, 61 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False): 62 """Initialize a simple base system.
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62 63 Keyword Arguments: 64 mem_mode -- String describing the memory mode (timing or atomic)
| 63 64 Keyword Arguments: 65 mem_mode -- String describing the memory mode (timing or atomic)
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| 66 mem_class -- Memory controller class to use
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65 cpu_class -- CPU class to use 66 num_cpus -- Number of CPUs to instantiate 67 checker -- Set to True to add checker CPUs 68 """ 69 self.mem_mode = mem_mode
| 67 cpu_class -- CPU class to use 68 num_cpus -- Number of CPUs to instantiate 69 checker -- Set to True to add checker CPUs 70 """ 71 self.mem_mode = mem_mode
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| 72 self.mem_class = mem_class
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70 self.cpu_class = cpu_class 71 self.num_cpus = num_cpus 72 self.checker = checker 73 74 def create_cpus(self): 75 """Return a list of CPU objects to add to a system.""" 76 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') 77 for i in range(self.num_cpus) ] 78 if self.checker: 79 for c in cpus: 80 c.addCheckerCpu() 81 return cpus 82 83 def create_caches_private(self, cpu): 84 """Add private caches to a CPU. 85 86 Arguments: 87 cpu -- CPU instance to work on. 88 """ 89 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), 90 L1Cache(size='32kB', assoc=4)) 91 92 def create_caches_shared(self, system): 93 """Add shared caches to a system. 94 95 Arguments: 96 system -- System to work on. 97 98 Returns: 99 A bus that CPUs should use to connect to the shared cache. 100 """ 101 system.toL2Bus = CoherentBus(clock='2GHz') 102 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) 103 system.l2c.cpu_side = system.toL2Bus.master 104 system.l2c.mem_side = system.membus.slave 105 return system.toL2Bus 106 107 def init_cpu(self, system, cpu, sha_bus): 108 """Initialize a CPU. 109 110 Arguments: 111 system -- System to work on. 112 cpu -- CPU to initialize. 113 """ 114 if not cpu.switched_out: 115 self.create_caches_private(cpu) 116 cpu.createInterruptController() 117 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 118 system.membus) 119 120 def init_kvm(self, system): 121 """Do KVM-specific system initialization. 122 123 Arguments: 124 system -- System to work on. 125 """ 126 system.vm = KvmVM() 127 128 def init_system(self, system): 129 """Initialize a system. 130 131 Arguments: 132 system -- System to initialize. 133 """ 134 system.clock = '1GHz' 135 system.cpu = self.create_cpus() 136 137 if _have_kvm_support and \ 138 any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 139 self.init_kvm(system) 140 141 sha_bus = self.create_caches_shared(system) 142 for cpu in system.cpu: 143 self.init_cpu(system, cpu, sha_bus) 144 145 @abstractmethod 146 def create_system(self): 147 """Create an return an initialized system.""" 148 pass 149 150 @abstractmethod 151 def create_root(self): 152 """Create and return a simulation root using the system 153 defined by this class.""" 154 pass 155
| 73 self.cpu_class = cpu_class 74 self.num_cpus = num_cpus 75 self.checker = checker 76 77 def create_cpus(self): 78 """Return a list of CPU objects to add to a system.""" 79 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') 80 for i in range(self.num_cpus) ] 81 if self.checker: 82 for c in cpus: 83 c.addCheckerCpu() 84 return cpus 85 86 def create_caches_private(self, cpu): 87 """Add private caches to a CPU. 88 89 Arguments: 90 cpu -- CPU instance to work on. 91 """ 92 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), 93 L1Cache(size='32kB', assoc=4)) 94 95 def create_caches_shared(self, system): 96 """Add shared caches to a system. 97 98 Arguments: 99 system -- System to work on. 100 101 Returns: 102 A bus that CPUs should use to connect to the shared cache. 103 """ 104 system.toL2Bus = CoherentBus(clock='2GHz') 105 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) 106 system.l2c.cpu_side = system.toL2Bus.master 107 system.l2c.mem_side = system.membus.slave 108 return system.toL2Bus 109 110 def init_cpu(self, system, cpu, sha_bus): 111 """Initialize a CPU. 112 113 Arguments: 114 system -- System to work on. 115 cpu -- CPU to initialize. 116 """ 117 if not cpu.switched_out: 118 self.create_caches_private(cpu) 119 cpu.createInterruptController() 120 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 121 system.membus) 122 123 def init_kvm(self, system): 124 """Do KVM-specific system initialization. 125 126 Arguments: 127 system -- System to work on. 128 """ 129 system.vm = KvmVM() 130 131 def init_system(self, system): 132 """Initialize a system. 133 134 Arguments: 135 system -- System to initialize. 136 """ 137 system.clock = '1GHz' 138 system.cpu = self.create_cpus() 139 140 if _have_kvm_support and \ 141 any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 142 self.init_kvm(system) 143 144 sha_bus = self.create_caches_shared(system) 145 for cpu in system.cpu: 146 self.init_cpu(system, cpu, sha_bus) 147 148 @abstractmethod 149 def create_system(self): 150 """Create an return an initialized system.""" 151 pass 152 153 @abstractmethod 154 def create_root(self): 155 """Create and return a simulation root using the system 156 defined by this class.""" 157 pass 158
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| 159class BaseSESystem(BaseSystem): 160 """Basic syscall-emulation builder.""" 161 162 def __init__(self, **kwargs): 163 BaseSystem.__init__(self, **kwargs) 164 165 def init_system(self, system): 166 BaseSystem.init_system(self, system) 167 168 def create_system(self): 169 system = System(physmem = self.mem_class(), 170 membus = CoherentBus(), 171 mem_mode = self.mem_mode) 172 system.system_port = system.membus.slave 173 system.physmem.port = system.membus.master 174 self.init_system(system) 175 return system 176 177 def create_root(self): 178 system = self.create_system() 179 m5.ticks.setGlobalFrequency('1THz') 180 return Root(full_system=False, system=system) 181 182class BaseSESystemUniprocessor(BaseSESystem): 183 """Basic syscall-emulation builder for uniprocessor systems. 184 185 Note: This class is only really needed to provide backwards 186 compatibility in existing test cases. 187 """ 188 189 def __init__(self, **kwargs): 190 BaseSESystem.__init__(self, **kwargs) 191 192 def create_caches_private(self, cpu): 193 # The atomic SE configurations do not use caches 194 if self.mem_mode == "timing": 195 # @todo We might want to revisit these rather enthusiastic L1 sizes 196 cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'), 197 L1Cache(size='256kB'), 198 L2Cache(size='2MB')) 199 200 def create_caches_shared(self, system): 201 return None 202
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156class BaseFSSystem(BaseSystem): 157 """Basic full system builder.""" 158 159 def __init__(self, **kwargs): 160 BaseSystem.__init__(self, **kwargs) 161 162 def init_system(self, system): 163 BaseSystem.init_system(self, system) 164 165 # create the iocache, which by default runs at the system clock 166 system.iocache = IOCache(addr_ranges=system.mem_ranges) 167 system.iocache.cpu_side = system.iobus.master 168 system.iocache.mem_side = system.membus.slave 169 170 def create_root(self): 171 system = self.create_system() 172 m5.ticks.setGlobalFrequency('1THz') 173 return Root(full_system=True, system=system) 174 175class BaseFSSystemUniprocessor(BaseFSSystem): 176 """Basic full system builder for uniprocessor systems. 177 178 Note: This class is only really needed to provide backwards 179 compatibility in existing test cases. 180 """ 181 182 def __init__(self, **kwargs): 183 BaseFSSystem.__init__(self, **kwargs) 184 185 def create_caches_private(self, cpu): 186 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), 187 L1Cache(size='32kB', assoc=4), 188 L2Cache(size='4MB', assoc=8)) 189 190 def create_caches_shared(self, system): 191 return None 192 193class BaseFSSwitcheroo(BaseFSSystem): 194 """Uniprocessor system prepared for CPU switching""" 195 196 def __init__(self, cpu_classes, **kwargs): 197 BaseFSSystem.__init__(self, **kwargs) 198 self.cpu_classes = tuple(cpu_classes) 199 200 def create_cpus(self): 201 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True) 202 for cclass in self.cpu_classes ] 203 cpus[0].switched_out = False 204 return cpus
| 203class BaseFSSystem(BaseSystem): 204 """Basic full system builder.""" 205 206 def __init__(self, **kwargs): 207 BaseSystem.__init__(self, **kwargs) 208 209 def init_system(self, system): 210 BaseSystem.init_system(self, system) 211 212 # create the iocache, which by default runs at the system clock 213 system.iocache = IOCache(addr_ranges=system.mem_ranges) 214 system.iocache.cpu_side = system.iobus.master 215 system.iocache.mem_side = system.membus.slave 216 217 def create_root(self): 218 system = self.create_system() 219 m5.ticks.setGlobalFrequency('1THz') 220 return Root(full_system=True, system=system) 221 222class BaseFSSystemUniprocessor(BaseFSSystem): 223 """Basic full system builder for uniprocessor systems. 224 225 Note: This class is only really needed to provide backwards 226 compatibility in existing test cases. 227 """ 228 229 def __init__(self, **kwargs): 230 BaseFSSystem.__init__(self, **kwargs) 231 232 def create_caches_private(self, cpu): 233 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), 234 L1Cache(size='32kB', assoc=4), 235 L2Cache(size='4MB', assoc=8)) 236 237 def create_caches_shared(self, system): 238 return None 239 240class BaseFSSwitcheroo(BaseFSSystem): 241 """Uniprocessor system prepared for CPU switching""" 242 243 def __init__(self, cpu_classes, **kwargs): 244 BaseFSSystem.__init__(self, **kwargs) 245 self.cpu_classes = tuple(cpu_classes) 246 247 def create_cpus(self): 248 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True) 249 for cclass in self.cpu_classes ] 250 cpus[0].switched_out = False 251 return cpus
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