1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45
46_have_kvm_support = 'BaseKvmCPU' in globals()
47
48class BaseSystem(object):
49 """Base system builder.
50
51 This class provides some basic functionality for creating an ARM
52 system with the usual peripherals (caches, GIC, etc.). It allows
53 customization by defining separate methods for different parts of
54 the initialization process.
55 """
56
57 __metaclass__ = ABCMeta
58
59 def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
60 num_cpus=1, checker=False):
61 """Initialize a simple ARM system.
62
63 Keyword Arguments:
64 mem_mode -- String describing the memory mode (timing or atomic)
65 cpu_class -- CPU class to use
66 num_cpus -- Number of CPUs to instantiate
67 checker -- Set to True to add checker CPUs
68 """
69 self.mem_mode = mem_mode
70 self.cpu_class = cpu_class
71 self.num_cpus = num_cpus
72 self.checker = checker
73
74 def create_cpus(self):
75 """Return a list of CPU objects to add to a system."""
76 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
77 for i in range(self.num_cpus) ]
78 if self.checker:
79 for c in cpus:
80 c.addCheckerCpu()
81 return cpus
82
83 def create_caches_private(self, cpu):
84 """Add private caches to a CPU.
85
86 Arguments:
87 cpu -- CPU instance to work on.
88 """
89 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
90 L1Cache(size='32kB', assoc=4))
91
92 def create_caches_shared(self, system):
93 """Add shared caches to a system.
94
95 Arguments:
96 system -- System to work on.
97
98 Returns:
99 A bus that CPUs should use to connect to the shared cache.
100 """
101 system.toL2Bus = CoherentBus(clock='2GHz')
102 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
103 system.l2c.cpu_side = system.toL2Bus.master
104 system.l2c.mem_side = system.membus.slave
105 return system.toL2Bus
106
107 def init_cpu(self, system, cpu, sha_bus):
108 """Initialize a CPU.
109
110 Arguments:
111 system -- System to work on.
112 cpu -- CPU to initialize.
113 """
114 if not cpu.switched_out:
115 self.create_caches_private(cpu)
116 cpu.createInterruptController()
117 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
118 system.membus)
119
120 def init_kvm(self, system):
121 """Do KVM-specific system initialization.
122
123 Arguments:
124 system -- System to work on.
125 """
126 system.vm = KvmVM()
127
128 def init_system(self, system):
129 """Initialize a system.
130
131 Arguments:
132 system -- System to initialize.
133 """
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45
46_have_kvm_support = 'BaseKvmCPU' in globals()
47
48class BaseSystem(object):
49 """Base system builder.
50
51 This class provides some basic functionality for creating an ARM
52 system with the usual peripherals (caches, GIC, etc.). It allows
53 customization by defining separate methods for different parts of
54 the initialization process.
55 """
56
57 __metaclass__ = ABCMeta
58
59 def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
60 num_cpus=1, checker=False):
61 """Initialize a simple ARM system.
62
63 Keyword Arguments:
64 mem_mode -- String describing the memory mode (timing or atomic)
65 cpu_class -- CPU class to use
66 num_cpus -- Number of CPUs to instantiate
67 checker -- Set to True to add checker CPUs
68 """
69 self.mem_mode = mem_mode
70 self.cpu_class = cpu_class
71 self.num_cpus = num_cpus
72 self.checker = checker
73
74 def create_cpus(self):
75 """Return a list of CPU objects to add to a system."""
76 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
77 for i in range(self.num_cpus) ]
78 if self.checker:
79 for c in cpus:
80 c.addCheckerCpu()
81 return cpus
82
83 def create_caches_private(self, cpu):
84 """Add private caches to a CPU.
85
86 Arguments:
87 cpu -- CPU instance to work on.
88 """
89 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
90 L1Cache(size='32kB', assoc=4))
91
92 def create_caches_shared(self, system):
93 """Add shared caches to a system.
94
95 Arguments:
96 system -- System to work on.
97
98 Returns:
99 A bus that CPUs should use to connect to the shared cache.
100 """
101 system.toL2Bus = CoherentBus(clock='2GHz')
102 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
103 system.l2c.cpu_side = system.toL2Bus.master
104 system.l2c.mem_side = system.membus.slave
105 return system.toL2Bus
106
107 def init_cpu(self, system, cpu, sha_bus):
108 """Initialize a CPU.
109
110 Arguments:
111 system -- System to work on.
112 cpu -- CPU to initialize.
113 """
114 if not cpu.switched_out:
115 self.create_caches_private(cpu)
116 cpu.createInterruptController()
117 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
118 system.membus)
119
120 def init_kvm(self, system):
121 """Do KVM-specific system initialization.
122
123 Arguments:
124 system -- System to work on.
125 """
126 system.vm = KvmVM()
127
128 def init_system(self, system):
129 """Initialize a system.
130
131 Arguments:
132 system -- System to initialize.
133 """
|
134 system.cpu = self.create_cpus()
135
136 if _have_kvm_support and \
137 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
138 self.init_kvm(system)
139
140 sha_bus = self.create_caches_shared(system)
141 for cpu in system.cpu:
142 self.init_cpu(system, cpu, sha_bus)
143
144 @abstractmethod
145 def create_system(self):
146 """Create an return an initialized system."""
147 pass
148
149 @abstractmethod
150 def create_root(self):
151 """Create and return a simulation root using the system
152 defined by this class."""
153 pass
154
155class BaseFSSystem(BaseSystem):
156 """Basic full system builder."""
157
158 def __init__(self, **kwargs):
159 BaseSystem.__init__(self, **kwargs)
160
161 def init_system(self, system):
162 BaseSystem.init_system(self, system)
163
164 # create the iocache, which by default runs at the system clock
165 system.iocache = IOCache(addr_ranges=system.mem_ranges)
166 system.iocache.cpu_side = system.iobus.master
167 system.iocache.mem_side = system.membus.slave
168
169 def create_root(self):
170 system = self.create_system()
171 m5.ticks.setGlobalFrequency('1THz')
172 return Root(full_system=True, system=system)
173
174class BaseFSSystemUniprocessor(BaseFSSystem):
175 """Basic full system builder for uniprocessor systems.
176
177 Note: This class is only really needed to provide backwards
178 compatibility in existing test cases.
179 """
180
181 def __init__(self, **kwargs):
182 BaseFSSystem.__init__(self, **kwargs)
183
184 def create_caches_private(self, cpu):
185 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
186 L1Cache(size='32kB', assoc=4),
187 L2Cache(size='4MB', assoc=8))
188
189 def create_caches_shared(self, system):
190 return None
191
192class BaseFSSwitcheroo(BaseFSSystem):
193 """Uniprocessor system prepared for CPU switching"""
194
195 def __init__(self, cpu_classes, **kwargs):
196 BaseFSSystem.__init__(self, **kwargs)
197 self.cpu_classes = tuple(cpu_classes)
198
199 def create_cpus(self):
200 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
201 for cclass in self.cpu_classes ]
202 cpus[0].switched_out = False
203 return cpus
| 135 system.cpu = self.create_cpus()
136
137 if _have_kvm_support and \
138 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
139 self.init_kvm(system)
140
141 sha_bus = self.create_caches_shared(system)
142 for cpu in system.cpu:
143 self.init_cpu(system, cpu, sha_bus)
144
145 @abstractmethod
146 def create_system(self):
147 """Create an return an initialized system."""
148 pass
149
150 @abstractmethod
151 def create_root(self):
152 """Create and return a simulation root using the system
153 defined by this class."""
154 pass
155
156class BaseFSSystem(BaseSystem):
157 """Basic full system builder."""
158
159 def __init__(self, **kwargs):
160 BaseSystem.__init__(self, **kwargs)
161
162 def init_system(self, system):
163 BaseSystem.init_system(self, system)
164
165 # create the iocache, which by default runs at the system clock
166 system.iocache = IOCache(addr_ranges=system.mem_ranges)
167 system.iocache.cpu_side = system.iobus.master
168 system.iocache.mem_side = system.membus.slave
169
170 def create_root(self):
171 system = self.create_system()
172 m5.ticks.setGlobalFrequency('1THz')
173 return Root(full_system=True, system=system)
174
175class BaseFSSystemUniprocessor(BaseFSSystem):
176 """Basic full system builder for uniprocessor systems.
177
178 Note: This class is only really needed to provide backwards
179 compatibility in existing test cases.
180 """
181
182 def __init__(self, **kwargs):
183 BaseFSSystem.__init__(self, **kwargs)
184
185 def create_caches_private(self, cpu):
186 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
187 L1Cache(size='32kB', assoc=4),
188 L2Cache(size='4MB', assoc=8))
189
190 def create_caches_shared(self, system):
191 return None
192
193class BaseFSSwitcheroo(BaseFSSystem):
194 """Uniprocessor system prepared for CPU switching"""
195
196 def __init__(self, cpu_classes, **kwargs):
197 BaseFSSystem.__init__(self, **kwargs)
198 self.cpu_classes = tuple(cpu_classes)
199
200 def create_cpus(self):
201 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
202 for cclass in self.cpu_classes ]
203 cpus[0].switched_out = False
204 return cpus
|