1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45
46class BaseSystem(object):
47 """Base system builder.
48
49 This class provides some basic functionality for creating an ARM
50 system with the usual peripherals (caches, GIC, etc.). It allows
51 customization by defining separate methods for different parts of
52 the initialization process.
53 """
54
55 __metaclass__ = ABCMeta
56
57 def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
58 num_cpus=1, checker=False):
59 """Initialize a simple ARM system.
60
61 Keyword Arguments:
62 mem_mode -- String describing the memory mode (timing or atomic)
63 cpu_class -- CPU class to use
64 num_cpus -- Number of CPUs to instantiate
65 checker -- Set to True to add checker CPUs
66 """
67 self.mem_mode = mem_mode
68 self.cpu_class = cpu_class
69 self.num_cpus = num_cpus
70 self.checker = checker
71
72 def create_cpus(self):
73 """Return a list of CPU objects to add to a system."""
74 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
75 for i in range(self.num_cpus) ]
76 if self.checker:
77 for c in cpus:
78 c.addCheckerCpu()
79 return cpus
80
81 def create_caches_private(self, cpu):
82 """Add private caches to a CPU.
83
84 Arguments:
85 cpu -- CPU instance to work on.
86 """
87 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
88 L1Cache(size='32kB', assoc=4))
89
90 def create_caches_shared(self, system):
91 """Add shared caches to a system.
92
93 Arguments:
94 system -- System to work on.
95
96 Returns:
97 A bus that CPUs should use to connect to the shared cache.
98 """
99 system.toL2Bus = CoherentBus(clock='2GHz')
100 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
101 system.l2c.cpu_side = system.toL2Bus.master
102 system.l2c.mem_side = system.membus.slave
103 return system.toL2Bus
104
105 def init_cpu(self, system, cpu):
106 """Initialize a CPU.
107
108 Arguments:
109 system -- System to work on.
110 cpu -- CPU to initialize.
111 """
112 cpu.createInterruptController()
113
114 def init_system(self, system):
115 """Initialize a system.
116
117 Arguments:
118 system -- System to initialize.
119 """
120 system.cpu = self.create_cpus()
121
122 sha_bus = self.create_caches_shared(system)
123 for cpu in system.cpu:
124 self.create_caches_private(cpu)
125 self.init_cpu(system, cpu)
126 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
127 system.membus)
128
129 @abstractmethod
130 def create_system(self):
131 """Create an return an initialized system."""
132 pass
133
134 @abstractmethod
135 def create_root(self):
136 """Create and return a simulation root using the system
137 defined by this class."""
138 pass
139
140class BaseFSSystem(BaseSystem):
141 """Basic full system builder."""
142
143 def __init__(self, **kwargs):
144 BaseSystem.__init__(self, **kwargs)
145
146 def init_system(self, system):
147 BaseSystem.init_system(self, system)
148
149 #create the iocache
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45
46class BaseSystem(object):
47 """Base system builder.
48
49 This class provides some basic functionality for creating an ARM
50 system with the usual peripherals (caches, GIC, etc.). It allows
51 customization by defining separate methods for different parts of
52 the initialization process.
53 """
54
55 __metaclass__ = ABCMeta
56
57 def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
58 num_cpus=1, checker=False):
59 """Initialize a simple ARM system.
60
61 Keyword Arguments:
62 mem_mode -- String describing the memory mode (timing or atomic)
63 cpu_class -- CPU class to use
64 num_cpus -- Number of CPUs to instantiate
65 checker -- Set to True to add checker CPUs
66 """
67 self.mem_mode = mem_mode
68 self.cpu_class = cpu_class
69 self.num_cpus = num_cpus
70 self.checker = checker
71
72 def create_cpus(self):
73 """Return a list of CPU objects to add to a system."""
74 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
75 for i in range(self.num_cpus) ]
76 if self.checker:
77 for c in cpus:
78 c.addCheckerCpu()
79 return cpus
80
81 def create_caches_private(self, cpu):
82 """Add private caches to a CPU.
83
84 Arguments:
85 cpu -- CPU instance to work on.
86 """
87 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
88 L1Cache(size='32kB', assoc=4))
89
90 def create_caches_shared(self, system):
91 """Add shared caches to a system.
92
93 Arguments:
94 system -- System to work on.
95
96 Returns:
97 A bus that CPUs should use to connect to the shared cache.
98 """
99 system.toL2Bus = CoherentBus(clock='2GHz')
100 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
101 system.l2c.cpu_side = system.toL2Bus.master
102 system.l2c.mem_side = system.membus.slave
103 return system.toL2Bus
104
105 def init_cpu(self, system, cpu):
106 """Initialize a CPU.
107
108 Arguments:
109 system -- System to work on.
110 cpu -- CPU to initialize.
111 """
112 cpu.createInterruptController()
113
114 def init_system(self, system):
115 """Initialize a system.
116
117 Arguments:
118 system -- System to initialize.
119 """
120 system.cpu = self.create_cpus()
121
122 sha_bus = self.create_caches_shared(system)
123 for cpu in system.cpu:
124 self.create_caches_private(cpu)
125 self.init_cpu(system, cpu)
126 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
127 system.membus)
128
129 @abstractmethod
130 def create_system(self):
131 """Create an return an initialized system."""
132 pass
133
134 @abstractmethod
135 def create_root(self):
136 """Create and return a simulation root using the system
137 defined by this class."""
138 pass
139
140class BaseFSSystem(BaseSystem):
141 """Basic full system builder."""
142
143 def __init__(self, **kwargs):
144 BaseSystem.__init__(self, **kwargs)
145
146 def init_system(self, system):
147 BaseSystem.init_system(self, system)
148
149 #create the iocache
|
151 system.iocache.cpu_side = system.iobus.master
152 system.iocache.mem_side = system.membus.slave
153
154 def create_root(self):
155 system = self.create_system()
156 m5.ticks.setGlobalFrequency('1THz')
157 return Root(full_system=True, system=system)
158
159class BaseFSSystemUniprocessor(BaseFSSystem):
160 """Basic full system builder for uniprocessor systems.
161
162 Note: This class is only really needed to provide backwards
163 compatibility in existing test cases.
164 """
165
166 def __init__(self, **kwargs):
167 BaseFSSystem.__init__(self, **kwargs)
168
169 def create_caches_private(self, cpu):
170 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
171 L1Cache(size='32kB', assoc=4),
172 L2Cache(size='4MB', assoc=8))
173
174 def create_caches_shared(self, system):
175 return None
| 151 system.iocache.cpu_side = system.iobus.master
152 system.iocache.mem_side = system.membus.slave
153
154 def create_root(self):
155 system = self.create_system()
156 m5.ticks.setGlobalFrequency('1THz')
157 return Root(full_system=True, system=system)
158
159class BaseFSSystemUniprocessor(BaseFSSystem):
160 """Basic full system builder for uniprocessor systems.
161
162 Note: This class is only really needed to provide backwards
163 compatibility in existing test cases.
164 """
165
166 def __init__(self, **kwargs):
167 BaseFSSystem.__init__(self, **kwargs)
168
169 def create_caches_private(self, cpu):
170 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
171 L1Cache(size='32kB', assoc=4),
172 L2Cache(size='4MB', assoc=8))
173
174 def create_caches_shared(self, system):
175 return None
|