1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39from abc import ABCMeta, abstractmethod
40import m5
41from m5.objects import *
42from m5.proxy import *
43m5.util.addToPath('../configs/common')
44import FSConfig
45from Caches import *
46
47_have_kvm_support = 'BaseKvmCPU' in globals()
48
49class BaseSystem(object):
50 """Base system builder.
51
52 This class provides some basic functionality for creating an ARM
53 system with the usual peripherals (caches, GIC, etc.). It allows
54 customization by defining separate methods for different parts of
55 the initialization process.
56 """
57
58 __metaclass__ = ABCMeta
59
60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
61 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False):
62 """Initialize a simple base system.
63
64 Keyword Arguments:
65 mem_mode -- String describing the memory mode (timing or atomic)
66 mem_class -- Memory controller class to use
67 cpu_class -- CPU class to use
68 num_cpus -- Number of CPUs to instantiate
69 checker -- Set to True to add checker CPUs
70 """
71 self.mem_mode = mem_mode
72 self.mem_class = mem_class
73 self.cpu_class = cpu_class
74 self.num_cpus = num_cpus
75 self.checker = checker
76
77 def create_cpus(self):
78 """Return a list of CPU objects to add to a system."""
79 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
80 for i in range(self.num_cpus) ]
81 if self.checker:
82 for c in cpus:
83 c.addCheckerCpu()
84 return cpus
85
86 def create_caches_private(self, cpu):
87 """Add private caches to a CPU.
88
89 Arguments:
90 cpu -- CPU instance to work on.
91 """
92 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
93 L1Cache(size='32kB', assoc=4))
94
95 def create_caches_shared(self, system):
96 """Add shared caches to a system.
97
98 Arguments:
99 system -- System to work on.
100
101 Returns:
102 A bus that CPUs should use to connect to the shared cache.
103 """
104 system.toL2Bus = CoherentBus(clock='2GHz')
105 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
106 system.l2c.cpu_side = system.toL2Bus.master
107 system.l2c.mem_side = system.membus.slave
108 return system.toL2Bus
109
110 def init_cpu(self, system, cpu, sha_bus):
111 """Initialize a CPU.
112
113 Arguments:
114 system -- System to work on.
115 cpu -- CPU to initialize.
116 """
117 if not cpu.switched_out:
118 self.create_caches_private(cpu)
119 cpu.createInterruptController()
120 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
121 system.membus)
122
123 def init_kvm(self, system):
124 """Do KVM-specific system initialization.
125
126 Arguments:
127 system -- System to work on.
128 """
129 system.vm = KvmVM()
130
131 def init_system(self, system):
132 """Initialize a system.
133
134 Arguments:
135 system -- System to initialize.
136 """
137 system.clock = '1GHz'
138 system.cpu = self.create_cpus()
139
140 if _have_kvm_support and \
141 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
142 self.init_kvm(system)
143
144 sha_bus = self.create_caches_shared(system)
145 for cpu in system.cpu:
146 self.init_cpu(system, cpu, sha_bus)
147
148 @abstractmethod
149 def create_system(self):
150 """Create an return an initialized system."""
151 pass
152
153 @abstractmethod
154 def create_root(self):
155 """Create and return a simulation root using the system
156 defined by this class."""
157 pass
158
159class BaseSESystem(BaseSystem):
160 """Basic syscall-emulation builder."""
161
162 def __init__(self, **kwargs):
163 BaseSystem.__init__(self, **kwargs)
164
165 def init_system(self, system):
166 BaseSystem.init_system(self, system)
167
168 def create_system(self):
169 system = System(physmem = self.mem_class(),
170 membus = CoherentBus(),
171 mem_mode = self.mem_mode)
172 system.system_port = system.membus.slave
173 system.physmem.port = system.membus.master
174 self.init_system(system)
175 return system
176
177 def create_root(self):
178 system = self.create_system()
179 m5.ticks.setGlobalFrequency('1THz')
180 return Root(full_system=False, system=system)
181
182class BaseSESystemUniprocessor(BaseSESystem):
183 """Basic syscall-emulation builder for uniprocessor systems.
184
185 Note: This class is only really needed to provide backwards
186 compatibility in existing test cases.
187 """
188
189 def __init__(self, **kwargs):
190 BaseSESystem.__init__(self, **kwargs)
191
192 def create_caches_private(self, cpu):
193 # The atomic SE configurations do not use caches
194 if self.mem_mode == "timing":
195 # @todo We might want to revisit these rather enthusiastic L1 sizes
196 cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
197 L1Cache(size='256kB'),
198 L2Cache(size='2MB'))
199
200 def create_caches_shared(self, system):
201 return None
202
203class BaseFSSystem(BaseSystem):
204 """Basic full system builder."""
205
206 def __init__(self, **kwargs):
207 BaseSystem.__init__(self, **kwargs)
208
209 def init_system(self, system):
210 BaseSystem.init_system(self, system)
211
212 # create the iocache, which by default runs at the system clock
213 system.iocache = IOCache(addr_ranges=system.mem_ranges)
214 system.iocache.cpu_side = system.iobus.master
215 system.iocache.mem_side = system.membus.slave
216
217 def create_root(self):
218 system = self.create_system()
219 m5.ticks.setGlobalFrequency('1THz')
220 return Root(full_system=True, system=system)
221
222class BaseFSSystemUniprocessor(BaseFSSystem):
223 """Basic full system builder for uniprocessor systems.
224
225 Note: This class is only really needed to provide backwards
226 compatibility in existing test cases.
227 """
228
229 def __init__(self, **kwargs):
230 BaseFSSystem.__init__(self, **kwargs)
231
232 def create_caches_private(self, cpu):
233 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
234 L1Cache(size='32kB', assoc=4),
235 L2Cache(size='4MB', assoc=8))
236
237 def create_caches_shared(self, system):
238 return None
239
240class BaseFSSwitcheroo(BaseFSSystem):
241 """Uniprocessor system prepared for CPU switching"""
242
243 def __init__(self, cpu_classes, **kwargs):
244 BaseFSSystem.__init__(self, **kwargs)
245 self.cpu_classes = tuple(cpu_classes)
246
247 def create_cpus(self):
248 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
249 for cclass in self.cpu_classes ]
250 cpus[0].switched_out = False
251 return cpus
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39from abc import ABCMeta, abstractmethod
40import m5
41from m5.objects import *
42from m5.proxy import *
43m5.util.addToPath('../configs/common')
44import FSConfig
45from Caches import *
46
47_have_kvm_support = 'BaseKvmCPU' in globals()
48
49class BaseSystem(object):
50 """Base system builder.
51
52 This class provides some basic functionality for creating an ARM
53 system with the usual peripherals (caches, GIC, etc.). It allows
54 customization by defining separate methods for different parts of
55 the initialization process.
56 """
57
58 __metaclass__ = ABCMeta
59
60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
61 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False):
62 """Initialize a simple base system.
63
64 Keyword Arguments:
65 mem_mode -- String describing the memory mode (timing or atomic)
66 mem_class -- Memory controller class to use
67 cpu_class -- CPU class to use
68 num_cpus -- Number of CPUs to instantiate
69 checker -- Set to True to add checker CPUs
70 """
71 self.mem_mode = mem_mode
72 self.mem_class = mem_class
73 self.cpu_class = cpu_class
74 self.num_cpus = num_cpus
75 self.checker = checker
76
77 def create_cpus(self):
78 """Return a list of CPU objects to add to a system."""
79 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
80 for i in range(self.num_cpus) ]
81 if self.checker:
82 for c in cpus:
83 c.addCheckerCpu()
84 return cpus
85
86 def create_caches_private(self, cpu):
87 """Add private caches to a CPU.
88
89 Arguments:
90 cpu -- CPU instance to work on.
91 """
92 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
93 L1Cache(size='32kB', assoc=4))
94
95 def create_caches_shared(self, system):
96 """Add shared caches to a system.
97
98 Arguments:
99 system -- System to work on.
100
101 Returns:
102 A bus that CPUs should use to connect to the shared cache.
103 """
104 system.toL2Bus = CoherentBus(clock='2GHz')
105 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
106 system.l2c.cpu_side = system.toL2Bus.master
107 system.l2c.mem_side = system.membus.slave
108 return system.toL2Bus
109
110 def init_cpu(self, system, cpu, sha_bus):
111 """Initialize a CPU.
112
113 Arguments:
114 system -- System to work on.
115 cpu -- CPU to initialize.
116 """
117 if not cpu.switched_out:
118 self.create_caches_private(cpu)
119 cpu.createInterruptController()
120 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
121 system.membus)
122
123 def init_kvm(self, system):
124 """Do KVM-specific system initialization.
125
126 Arguments:
127 system -- System to work on.
128 """
129 system.vm = KvmVM()
130
131 def init_system(self, system):
132 """Initialize a system.
133
134 Arguments:
135 system -- System to initialize.
136 """
137 system.clock = '1GHz'
138 system.cpu = self.create_cpus()
139
140 if _have_kvm_support and \
141 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
142 self.init_kvm(system)
143
144 sha_bus = self.create_caches_shared(system)
145 for cpu in system.cpu:
146 self.init_cpu(system, cpu, sha_bus)
147
148 @abstractmethod
149 def create_system(self):
150 """Create an return an initialized system."""
151 pass
152
153 @abstractmethod
154 def create_root(self):
155 """Create and return a simulation root using the system
156 defined by this class."""
157 pass
158
159class BaseSESystem(BaseSystem):
160 """Basic syscall-emulation builder."""
161
162 def __init__(self, **kwargs):
163 BaseSystem.__init__(self, **kwargs)
164
165 def init_system(self, system):
166 BaseSystem.init_system(self, system)
167
168 def create_system(self):
169 system = System(physmem = self.mem_class(),
170 membus = CoherentBus(),
171 mem_mode = self.mem_mode)
172 system.system_port = system.membus.slave
173 system.physmem.port = system.membus.master
174 self.init_system(system)
175 return system
176
177 def create_root(self):
178 system = self.create_system()
179 m5.ticks.setGlobalFrequency('1THz')
180 return Root(full_system=False, system=system)
181
182class BaseSESystemUniprocessor(BaseSESystem):
183 """Basic syscall-emulation builder for uniprocessor systems.
184
185 Note: This class is only really needed to provide backwards
186 compatibility in existing test cases.
187 """
188
189 def __init__(self, **kwargs):
190 BaseSESystem.__init__(self, **kwargs)
191
192 def create_caches_private(self, cpu):
193 # The atomic SE configurations do not use caches
194 if self.mem_mode == "timing":
195 # @todo We might want to revisit these rather enthusiastic L1 sizes
196 cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
197 L1Cache(size='256kB'),
198 L2Cache(size='2MB'))
199
200 def create_caches_shared(self, system):
201 return None
202
203class BaseFSSystem(BaseSystem):
204 """Basic full system builder."""
205
206 def __init__(self, **kwargs):
207 BaseSystem.__init__(self, **kwargs)
208
209 def init_system(self, system):
210 BaseSystem.init_system(self, system)
211
212 # create the iocache, which by default runs at the system clock
213 system.iocache = IOCache(addr_ranges=system.mem_ranges)
214 system.iocache.cpu_side = system.iobus.master
215 system.iocache.mem_side = system.membus.slave
216
217 def create_root(self):
218 system = self.create_system()
219 m5.ticks.setGlobalFrequency('1THz')
220 return Root(full_system=True, system=system)
221
222class BaseFSSystemUniprocessor(BaseFSSystem):
223 """Basic full system builder for uniprocessor systems.
224
225 Note: This class is only really needed to provide backwards
226 compatibility in existing test cases.
227 """
228
229 def __init__(self, **kwargs):
230 BaseFSSystem.__init__(self, **kwargs)
231
232 def create_caches_private(self, cpu):
233 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
234 L1Cache(size='32kB', assoc=4),
235 L2Cache(size='4MB', assoc=8))
236
237 def create_caches_shared(self, system):
238 return None
239
240class BaseFSSwitcheroo(BaseFSSystem):
241 """Uniprocessor system prepared for CPU switching"""
242
243 def __init__(self, cpu_classes, **kwargs):
244 BaseFSSystem.__init__(self, **kwargs)
245 self.cpu_classes = tuple(cpu_classes)
246
247 def create_cpus(self):
248 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
249 for cclass in self.cpu_classes ]
250 cpus[0].switched_out = False
251 return cpus