simple.S (7843:fb777f10f3df) | simple.S (8280:5dddde1126c2) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 30 unchanged lines hidden (view full) --- 39 40/************************************************************************* 41 * Super simple bootloader 42 * Preserve loaded values that we need to pass to the kernel (r0, r1, r2) 43 * Additionally M5 puts the kernel start address in r3 44 * 45 * Upon executing this code: 46 * r0 = 0, r1 = machine number, r2 = atags ptr | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 30 unchanged lines hidden (view full) --- 39 40/************************************************************************* 41 * Super simple bootloader 42 * Preserve loaded values that we need to pass to the kernel (r0, r1, r2) 43 * Additionally M5 puts the kernel start address in r3 44 * 45 * Upon executing this code: 46 * r0 = 0, r1 = machine number, r2 = atags ptr |
47 * r3 = kernel start address | 47 * r3 = kernel start address, r4 = GIC address, r5 = flag register address |
48 * 49 * CPU 0 should branch to the kernel start address and it's done with 50 * the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends 51 * an IPI the slave CPUs reads a register which CPU0 has programmed with the 52 * boot address for the secondary cpu 53 **************************************************************************/ 54.text 55.globl _start 56.extern main 57_start: 58_entry: | 48 * 49 * CPU 0 should branch to the kernel start address and it's done with 50 * the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends 51 * an IPI the slave CPUs reads a register which CPU0 has programmed with the 52 * boot address for the secondary cpu 53 **************************************************************************/ 54.text 55.globl _start 56.extern main 57_start: 58_entry: |
59 mrc p15, 0, r4, c0, c0, 5 // get the MPIDR register 60 uxtb r4, r4 // isolate the lower 8 bits (affinity lvl 1) 61 adds r4, r4, #0 // set flags for branch | 59 b bootldr // All the interrupt vectors jump to the boot loader 60 b bootldr 61 b bootldr 62 b bootldr 63 b bootldr 64 b bootldr 65 b bootldr 66 b bootldr 67 b bootldr 68 69bootldr: 70 mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register 71 uxtb r8, r8 // isolate the lower 8 bits (affinity lvl 1) 72 adds r8, r8, #0 // set flags for branch |
62 bxeq r3 // if it's 0 (CPU 0), branch to kernel | 73 bxeq r3 // if it's 0 (CPU 0), branch to kernel |
74 mov r8, #1 75 str r8, [r4, #0] // Enable CPU interface on GIC 76 wfi // wait for an interrupt |
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63pen: | 77pen: |
64 wfi // otherwise wait for an interrupt 65 mov r4, #0x30 // Build address of the system controller 66 movt r4, #0x1000 // flag register r4 = 0x10000030 67 ldr r5, [r4] // load the value 68 movs r5, r5 // set the flags on this value | 78 ldr r8, [r5] // load the value 79 movs r8, r8 // set the flags on this value |
69 beq pen // if it's zero try again | 80 beq pen // if it's zero try again |
70 bx r5 // Jump to where we've been told | 81 bx r8 // Jump to where we've been told |
71 bkpt // We should never get here | 82 bkpt // We should never get here |