vexpress_gem5_v2_base.dtsi (14179:9e01b57898e0) vexpress_gem5_v2_base.dtsi (14281:c2a55039dc4d)
1/*
2 * Copyright (c) 2015-2017, 2019 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44 redistributor-stride = <0x0 0x40000>; // 256kB stride
45 reg = <0x0 0x2c000000 0x0 0x10000
46 0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...)
47 0x0 0x0 0x0 0x0>;
48 interrupts = <1 9 0xf04>;
49 #size-cells = <0x2>;
50 linux,phandle = <0x1>;
51 phandle = <0x1>;
1/*
2 * Copyright (c) 2015-2017, 2019 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44 redistributor-stride = <0x0 0x40000>; // 256kB stride
45 reg = <0x0 0x2c000000 0x0 0x10000
46 0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...)
47 0x0 0x0 0x0 0x0>;
48 interrupts = <1 9 0xf04>;
49 #size-cells = <0x2>;
50 linux,phandle = <0x1>;
51 phandle = <0x1>;
52
53 gic-its@2e010000 {
54 compatible = "arm,gic-v3-its";
55 msi-controller;
56 #msi-cells = <1>;
57 reg = <0x0 0x2e010000 0 0x20000>;
58 };
52 };
53
54 timer {
55 compatible = "arm,cortex-a15-timer",
56 "arm,armv7-timer";
57 interrupts = <1 13 0xf08>,
58 <1 14 0xf08>,
59 <1 11 0xf08>,

--- 136 unchanged lines hidden --- 		59 };
60
61 timer {
62 compatible = "arm,cortex-a15-timer",
63 "arm,armv7-timer";
64 interrupts = <1 13 0xf08>,
65 <1 14 0xf08>,
66 <1 11 0xf08>,

--- 136 unchanged lines hidden ---