1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31/ {
32 arm,hbi = <0x0>;
33 arm,vexpress,site = <0xf>;
34 interrupt-parent = <&gic>;
35 #address-cells = <2>;
36 #size-cells = <2>;
37
38 gic: interrupt-controller@2c000000 {
39 compatible = "arm,gic-v3";
40 #interrupt-cells = <0x3>;
41 #address-cells = <0x2>;
42 interrupt-controller;
| 1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31/ {
32 arm,hbi = <0x0>;
33 arm,vexpress,site = <0xf>;
34 interrupt-parent = <&gic>;
35 #address-cells = <2>;
36 #size-cells = <2>;
37
38 gic: interrupt-controller@2c000000 {
39 compatible = "arm,gic-v3";
40 #interrupt-cells = <0x3>;
41 #address-cells = <0x2>;
42 interrupt-controller;
|
46 0x0 0x0 0x0 0x0>;
47 interrupts = <1 9 0xf04>;
48 #size-cells = <0x2>;
49 linux,phandle = <0x1>;
50 phandle = <0x1>;
51 };
52
53 timer {
54 compatible = "arm,cortex-a15-timer",
55 "arm,armv7-timer";
56 interrupts = <1 13 0xf08>,
57 <1 14 0xf08>,
58 <1 11 0xf08>;
59 clocks = <&osc_sys>;
60 clock-names="apb_pclk";
61 };
62
63 pci {
64 compatible = "pci-host-ecam-generic";
65 device_type = "pci";
66 #address-cells = <0x3>;
67 #size-cells = <0x2>;
68 #interrupt-cells = <0x1>;
69
70 reg = <0x0 0x30000000 0x0 0x10000000>;
71
72 ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
73 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
74
75 /*
76 child unit address, #cells = #address-cells
77 child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4)
78 interrupt-parent, phandle
79 parent unit address, #cells = #address-cells@gic
80 parent interrupt specifier, #cells = #interrupt-cells@gic
81 */
82 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x44 0x1
83 0x800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x45 0x1
84 0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x46 0x1
85 0x1800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x47 0x1>;
86
87 interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
88 dma-coherent;
89 };
90
91 kmi@1c060000 {
92 compatible = "arm,pl050", "arm,primecell";
93 reg = <0x0 0x1c060000 0x0 0x1000>;
94 interrupts = <0 12 4>;
95 clocks = <&v2m_clk24mhz>, <&osc_smb>;
96 clock-names = "KMIREFCLK", "apb_pclk";
97 };
98
99 kmi@1c070000 {
100 compatible = "arm,pl050", "arm,primecell";
101 reg = <0x0 0x1c070000 0x0 0x1000>;
102 interrupts = <0 13 4>;
103 clocks = <&v2m_clk24mhz>, <&osc_smb>;
104 clock-names = "KMIREFCLK", "apb_pclk";
105 };
106
107 uart0: uart@1c090000 {
108 compatible = "arm,pl011", "arm,primecell";
109 reg = <0x0 0x1c090000 0x0 0x1000>;
110 interrupts = <0 5 4>;
111 clocks = <&osc_peripheral>, <&osc_smb>;
112 clock-names = "uartclk", "apb_pclk";
113 };
114
115 rtc@1c170000 {
116 compatible = "arm,pl031", "arm,primecell";
117 reg = <0x0 0x1c170000 0x0 0x1000>;
118 interrupts = <0 4 4>;
119 clocks = <&osc_smb>;
120 clock-names = "apb_pclk";
121 };
122
123 v2m_clk24mhz: clk24mhz {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <24000000>;
127 clock-output-names = "v2m:clk24mhz";
128 };
129
130
131 v2m_sysreg: sysreg@1c010000 {
132 compatible = "arm,vexpress-sysreg";
133 reg = <0 0x1c010000 0x0 0x1000>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 };
137
138 vio@1c130000 {
139 compatible = "virtio,mmio";
140 reg = <0 0x1c130000 0x0 0x1000>;
141 interrupts = <0 42 4>;
142 };
143
144 vio@1c140000 {
145 compatible = "virtio,mmio";
146 reg = <0 0x1c140000 0x0 0x1000>;
147 interrupts = <0 43 4>;
148 };
149
150 dcc {
151 compatible = "arm,vexpress,config-bus";
152 arm,vexpress,config-bridge = <&v2m_sysreg>;
153
154 osc_pxl: osc@5 {
155 compatible = "arm,vexpress-osc";
156 arm,vexpress-sysreg,func = <1 5>;
157 freq-range = <23750000 1000000000>;
158 #clock-cells = <0>;
159 clock-output-names = "oscclk5";
160 };
161
162 osc_smb: osc@6 {
163 compatible = "arm,vexpress-osc";
164 arm,vexpress-sysreg,func = <1 6>;
165 freq-range = <20000000 50000000>;
166 #clock-cells = <0>;
167 clock-output-names = "oscclk6";
168 };
169
170 osc_sys: osc@7 {
171 compatible = "arm,vexpress-osc";
172 arm,vexpress-sysreg,func = <1 7>;
173 freq-range = <20000000 60000000>;
174 #clock-cells = <0>;
175 clock-output-names = "oscclk7";
176 };
177 };
178
179
180 mcc {
181 compatible = "arm,vexpress,config-bus";
182 arm,vexpress,config-bridge = <&v2m_sysreg>;
183 arm,vexpress,site = <0>;
184
185 osc_peripheral: osc@2 {
186 compatible = "arm,vexpress-osc";
187 arm,vexpress-sysreg,func = <1 2>;
188 freq-range = <24000000 24000000>;
189 #clock-cells = <0>;
190 clock-output-names = "v2m:oscclk2";
191 };
192 };
193};
| 46 0x0 0x0 0x0 0x0>;
47 interrupts = <1 9 0xf04>;
48 #size-cells = <0x2>;
49 linux,phandle = <0x1>;
50 phandle = <0x1>;
51 };
52
53 timer {
54 compatible = "arm,cortex-a15-timer",
55 "arm,armv7-timer";
56 interrupts = <1 13 0xf08>,
57 <1 14 0xf08>,
58 <1 11 0xf08>;
59 clocks = <&osc_sys>;
60 clock-names="apb_pclk";
61 };
62
63 pci {
64 compatible = "pci-host-ecam-generic";
65 device_type = "pci";
66 #address-cells = <0x3>;
67 #size-cells = <0x2>;
68 #interrupt-cells = <0x1>;
69
70 reg = <0x0 0x30000000 0x0 0x10000000>;
71
72 ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
73 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
74
75 /*
76 child unit address, #cells = #address-cells
77 child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4)
78 interrupt-parent, phandle
79 parent unit address, #cells = #address-cells@gic
80 parent interrupt specifier, #cells = #interrupt-cells@gic
81 */
82 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x44 0x1
83 0x800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x45 0x1
84 0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x46 0x1
85 0x1800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x47 0x1>;
86
87 interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
88 dma-coherent;
89 };
90
91 kmi@1c060000 {
92 compatible = "arm,pl050", "arm,primecell";
93 reg = <0x0 0x1c060000 0x0 0x1000>;
94 interrupts = <0 12 4>;
95 clocks = <&v2m_clk24mhz>, <&osc_smb>;
96 clock-names = "KMIREFCLK", "apb_pclk";
97 };
98
99 kmi@1c070000 {
100 compatible = "arm,pl050", "arm,primecell";
101 reg = <0x0 0x1c070000 0x0 0x1000>;
102 interrupts = <0 13 4>;
103 clocks = <&v2m_clk24mhz>, <&osc_smb>;
104 clock-names = "KMIREFCLK", "apb_pclk";
105 };
106
107 uart0: uart@1c090000 {
108 compatible = "arm,pl011", "arm,primecell";
109 reg = <0x0 0x1c090000 0x0 0x1000>;
110 interrupts = <0 5 4>;
111 clocks = <&osc_peripheral>, <&osc_smb>;
112 clock-names = "uartclk", "apb_pclk";
113 };
114
115 rtc@1c170000 {
116 compatible = "arm,pl031", "arm,primecell";
117 reg = <0x0 0x1c170000 0x0 0x1000>;
118 interrupts = <0 4 4>;
119 clocks = <&osc_smb>;
120 clock-names = "apb_pclk";
121 };
122
123 v2m_clk24mhz: clk24mhz {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <24000000>;
127 clock-output-names = "v2m:clk24mhz";
128 };
129
130
131 v2m_sysreg: sysreg@1c010000 {
132 compatible = "arm,vexpress-sysreg";
133 reg = <0 0x1c010000 0x0 0x1000>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 };
137
138 vio@1c130000 {
139 compatible = "virtio,mmio";
140 reg = <0 0x1c130000 0x0 0x1000>;
141 interrupts = <0 42 4>;
142 };
143
144 vio@1c140000 {
145 compatible = "virtio,mmio";
146 reg = <0 0x1c140000 0x0 0x1000>;
147 interrupts = <0 43 4>;
148 };
149
150 dcc {
151 compatible = "arm,vexpress,config-bus";
152 arm,vexpress,config-bridge = <&v2m_sysreg>;
153
154 osc_pxl: osc@5 {
155 compatible = "arm,vexpress-osc";
156 arm,vexpress-sysreg,func = <1 5>;
157 freq-range = <23750000 1000000000>;
158 #clock-cells = <0>;
159 clock-output-names = "oscclk5";
160 };
161
162 osc_smb: osc@6 {
163 compatible = "arm,vexpress-osc";
164 arm,vexpress-sysreg,func = <1 6>;
165 freq-range = <20000000 50000000>;
166 #clock-cells = <0>;
167 clock-output-names = "oscclk6";
168 };
169
170 osc_sys: osc@7 {
171 compatible = "arm,vexpress-osc";
172 arm,vexpress-sysreg,func = <1 7>;
173 freq-range = <20000000 60000000>;
174 #clock-cells = <0>;
175 clock-output-names = "oscclk7";
176 };
177 };
178
179
180 mcc {
181 compatible = "arm,vexpress,config-bus";
182 arm,vexpress,config-bridge = <&v2m_sysreg>;
183 arm,vexpress,site = <0>;
184
185 osc_peripheral: osc@2 {
186 compatible = "arm,vexpress-osc";
187 arm,vexpress-sysreg,func = <1 2>;
188 freq-range = <24000000 24000000>;
189 #clock-cells = <0>;
190 clock-output-names = "v2m:oscclk2";
191 };
192 };
193};
|