1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35#include CONF_PLATFORM
36
37#define CPU(n) \
38 cpu@ ## n { \
39 device_type = "cpu"; \
40 compatible = "gem5,armv8", "arm,armv8"; \
41 reg = < n >; \
42 enable-method = "spin-table"; \
43 cpu-release-addr = <0 0x8000fff8>; \
44 };
45
46/ {
47 model = "V2P-AARCH64";
48 compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
49
50 memory@80000000 {
51 device_type = "memory";
52 reg = <0 0x80000000 0x4 0x00000000>;
53 };
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 #if CONF_CPUS > 0
60 CPU(0)
61 #endif
62 #if CONF_CPUS > 1
63 CPU(1)
64 #endif
65 #if CONF_CPUS > 2
66 CPU(2)
67 #endif
68 #if CONF_CPUS > 3
69 CPU(3)
70 #endif
71 #if CONF_CPUS > 4
72 CPU(4)
73 #endif
74 #if CONF_CPUS > 5
75 CPU(5)
76 #endif
77 #if CONF_CPUS > 6
78 CPU(6)
79 #endif
80 #if CONF_CPUS > 7
81 CPU(7)
82 #endif
83 #if CONF_CPUS > 8
84 CPU(8)
85 #endif
86 #if CONF_CPUS > 9
87 CPU(9)
88 #endif
89 #if CONF_CPUS > 10
90 CPU(10)
91 #endif
92 #if CONF_CPUS > 11
93 CPU(11)
94 #endif
95 #if CONF_CPUS > 12
96 CPU(12)
97 #endif
98 #if CONF_CPUS > 13
99 CPU(13)
100 #endif
101 #if CONF_CPUS > 14
102 CPU(14)
103 #endif
104 #if CONF_CPUS > 15
105 CPU(15)
106 #endif
107 #if CONF_CPUS > 16
108 #error Unsupported number of CPUs
109 #endif
110 };
111
112 virt-encoder {
113 compatible = "drm,virtual-encoder";
114 port {
| 1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35#include CONF_PLATFORM
36
37#define CPU(n) \
38 cpu@ ## n { \
39 device_type = "cpu"; \
40 compatible = "gem5,armv8", "arm,armv8"; \
41 reg = < n >; \
42 enable-method = "spin-table"; \
43 cpu-release-addr = <0 0x8000fff8>; \
44 };
45
46/ {
47 model = "V2P-AARCH64";
48 compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
49
50 memory@80000000 {
51 device_type = "memory";
52 reg = <0 0x80000000 0x4 0x00000000>;
53 };
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 #if CONF_CPUS > 0
60 CPU(0)
61 #endif
62 #if CONF_CPUS > 1
63 CPU(1)
64 #endif
65 #if CONF_CPUS > 2
66 CPU(2)
67 #endif
68 #if CONF_CPUS > 3
69 CPU(3)
70 #endif
71 #if CONF_CPUS > 4
72 CPU(4)
73 #endif
74 #if CONF_CPUS > 5
75 CPU(5)
76 #endif
77 #if CONF_CPUS > 6
78 CPU(6)
79 #endif
80 #if CONF_CPUS > 7
81 CPU(7)
82 #endif
83 #if CONF_CPUS > 8
84 CPU(8)
85 #endif
86 #if CONF_CPUS > 9
87 CPU(9)
88 #endif
89 #if CONF_CPUS > 10
90 CPU(10)
91 #endif
92 #if CONF_CPUS > 11
93 CPU(11)
94 #endif
95 #if CONF_CPUS > 12
96 CPU(12)
97 #endif
98 #if CONF_CPUS > 13
99 CPU(13)
100 #endif
101 #if CONF_CPUS > 14
102 CPU(14)
103 #endif
104 #if CONF_CPUS > 15
105 CPU(15)
106 #endif
107 #if CONF_CPUS > 16
108 #error Unsupported number of CPUs
109 #endif
110 };
111
112 virt-encoder {
113 compatible = "drm,virtual-encoder";
114 port {
|