| boot.S (13509:e9fd7d157c80) | boot.S (14113:a443e7bca88b) |
|---|---|
| 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 76 unchanged lines hidden (view full) --- 85 mov w0, #~0 // Grp1 interrupts 86 str w0, [x1], #4 87 b.ne 2f // Only local interrupts for secondary CPUs 88 ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR 89 str w0, [x1], #4 90 str w0, [x1], #4 91 str w0, [x1], #4 92 | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 76 unchanged lines hidden (view full) --- 85 mov w0, #~0 // Grp1 interrupts 86 str w0, [x1], #4 87 b.ne 2f // Only local interrupts for secondary CPUs 88 ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR 89 str w0, [x1], #4 90 str w0, [x1], #4 91 str w0, [x1], #4 92 |
| 93 /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */ 94 mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3 95 orr x10, x10, #0xf // enable 0xf 96 msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3 97 isb |
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| 93 942: mov x0, #1 95 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable 96 msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable 97#else 98 tst x0, x1 // check for cpuid==zero 99 b.ne 1f // secondary CPU 100 --- 91 unchanged lines hidden --- | 98 992: mov x0, #1 100 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable 101 msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable 102#else 103 tst x0, x1 // check for cpuid==zero 104 b.ne 1f // secondary CPU 105 --- 91 unchanged lines hidden --- |