boot.S (12271:fcd15e59fcd5) boot.S (13509:e9fd7d157c80)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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62 * Check for the primary CPU to avoid a race on the distributor
63 * registers.
64 */
65 mrs x0, mpidr_el1
66 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
67 // Test the the MPIDR_EL1 register against 0xff00ffffff to
68 // extract the primary CPU.
69 ldr x1, =0xff00ffffff
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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62 * Check for the primary CPU to avoid a race on the distributor
63 * registers.
64 */
65 mrs x0, mpidr_el1
66 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
67 // Test the the MPIDR_EL1 register against 0xff00ffffff to
68 // extract the primary CPU.
69 ldr x1, =0xff00ffffff
70#ifdef GICV3
71 and x2, x0, #0xff // use Aff0 as cpuid for now...
72 tst x0, x1 // check for cpuid==zero
73 b.ne 1f // secondary CPU
74
75 ldr x1, =GIC_DIST_BASE // GICD_CTLR
76 mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
77 str w0, [x1]
78
79
801: ldr x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0
81 // 128K for each redistributor, 256K strided...
82 mov x3, #1 << 18 // GICv4
83 mul x3, x3, x2
84 add x1, x1, x3
85 mov w0, #~0 // Grp1 interrupts
86 str w0, [x1], #4
87 b.ne 2f // Only local interrupts for secondary CPUs
88 ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
89 str w0, [x1], #4
90 str w0, [x1], #4
91 str w0, [x1], #4
92
93
942: mov x0, #1
95 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
96 msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
97#else
70 tst x0, x1 // check for cpuid==zero
71 b.ne 1f // secondary CPU
72
73 ldr x1, =GIC_DIST_BASE // GICD_CTLR
74 mov w0, #3 // EnableGrp0 | EnableGrp1
75 str w0, [x1]
76
771: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR

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83
842: ldr x1, =GIC_CPU_BASE // GICC_CTLR
85 ldr w0, [x1]
86 mov w0, #3 // EnableGrp0 | EnableGrp1
87 str w0, [x1]
88
89 mov w0, #1 << 7 // allow NS access to GICC_PMR
90 str w0, [x1, #4] // GICC_PMR
98 tst x0, x1 // check for cpuid==zero
99 b.ne 1f // secondary CPU
100
101 ldr x1, =GIC_DIST_BASE // GICD_CTLR
102 mov w0, #3 // EnableGrp0 | EnableGrp1
103 str w0, [x1]
104
1051: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR

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111
1122: ldr x1, =GIC_CPU_BASE // GICC_CTLR
113 ldr w0, [x1]
114 mov w0, #3 // EnableGrp0 | EnableGrp1
115 str w0, [x1]
116
117 mov w0, #1 << 7 // allow NS access to GICC_PMR
118 str w0, [x1, #4] // GICC_PMR
119#endif
91
92 msr sctlr_el2, xzr
93
94 /*
95 * Prepare the switch to the EL2_SP1 mode from EL3
96 */
97 ldr x0, =start_ns // Return after mode switch
98 mov x1, #0x3c9 // EL2_SP1 | D | A | I | F

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121 msr sctlr_el2, xzr
122
123 /*
124 * Prepare the switch to the EL2_SP1 mode from EL3
125 */
126 ldr x0, =start_ns // Return after mode switch
127 mov x1, #0x3c9 // EL2_SP1 | D | A | I | F

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