boot.S (10037:5cac77888310) boot.S (11258:9214b39401aa)
1/*
2 * boot.S - simple register setup code for stand-alone Linux booting
3 *
4 * Copyright (C) 2012 ARM Limited. All rights reserved.
5 *
6 * Use of this source code is governed by a BSD-style license that can be
7 * found in the LICENSE.txt file.
8 */

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29 ldr x0, =CNTFRQ
30 msr cntfrq_el0, x0
31
32 /*
33 * Check for the primary CPU to avoid a race on the distributor
34 * registers.
35 */
36 mrs x0, mpidr_el1
1/*
2 * boot.S - simple register setup code for stand-alone Linux booting
3 *
4 * Copyright (C) 2012 ARM Limited. All rights reserved.
5 *
6 * Use of this source code is governed by a BSD-style license that can be
7 * found in the LICENSE.txt file.
8 */

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29 ldr x0, =CNTFRQ
30 msr cntfrq_el0, x0
31
32 /*
33 * Check for the primary CPU to avoid a race on the distributor
34 * registers.
35 */
36 mrs x0, mpidr_el1
37 tst x0, #15
38 b.ne 1f // secondary CPU
37 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
38 // Test the the MPIDR_EL1 register against 0xff00ffffff to
39 // extract the primary CPU.
40 ldr x1, =0xff00ffffff
41 tst x0, x1 // check for cpuid==zero
42 b.ne 1f // secondary CPU
39
40 ldr x1, =GIC_DIST_BASE // GICD_CTLR
41 mov w0, #3 // EnableGrp0 | EnableGrp1
42 str w0, [x1]
43
441: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
45 mov w0, #~0 // Grp1 interrupts
46 str w0, [x1], #4

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72 * Kernel parameters
73 */
74 mov x0, xzr
75 mov x1, xzr
76 mov x2, xzr
77 mov x3, xzr
78
79 mrs x4, mpidr_el1
43
44 ldr x1, =GIC_DIST_BASE // GICD_CTLR
45 mov w0, #3 // EnableGrp0 | EnableGrp1
46 str w0, [x1]
47
481: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
49 mov w0, #~0 // Grp1 interrupts
50 str w0, [x1], #4

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76 * Kernel parameters
77 */
78 mov x0, xzr
79 mov x1, xzr
80 mov x2, xzr
81 mov x3, xzr
82
83 mrs x4, mpidr_el1
80 tst x4, #15
81 b.eq 2f
84 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
85 // Test the the MPIDR_EL1 register against 0xff00ffffff to
86 // extract the primary CPU.
87 ldr x1, =0xff00ffffff
88 tst x4, x1 // check for cpuid==zero
89 mov x1, xzr // load previous 'xzr' value back to x1
90 b.eq 2f // secondary CPU
82
83 /*
84 * Secondary CPUs
85 */
861: wfe
87 ldr x4, =PHYS_OFFSET + 0xfff8
88 ldr x4, [x4]
89 cbz x4, 1b

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92 /*
93 * Secondary CPUs
94 */
951: wfe
96 ldr x4, =PHYS_OFFSET + 0xfff8
97 ldr x4, [x4]
98 cbz x4, 1b

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