1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
38
39 .text
40
41 .globl _start
42_start:
43 /*
44 * EL3 initialisation
45 */
46 mrs x0, CurrentEL
47 cmp x0, #0xc // EL3?
48 b.ne start_ns // skip EL3 initialisation
49
50 mov x0, #0x30 // RES1
51 orr x0, x0, #(1 << 0) // Non-secure EL1
52 orr x0, x0, #(1 << 8) // HVC enable
53 orr x0, x0, #(1 << 10) // 64-bit EL2
54 msr scr_el3, x0
55
56 msr cptr_el3, xzr // Disable copro. traps to EL3
57
58 ldr x0, =CNTFRQ
59 msr cntfrq_el0, x0
60
61 /*
62 * Check for the primary CPU to avoid a race on the distributor
63 * registers.
64 */
65 mrs x0, mpidr_el1
66 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
67 // Test the the MPIDR_EL1 register against 0xff00ffffff to
68 // extract the primary CPU.
69 ldr x1, =0xff00ffffff
70#ifdef GICV3
71 and x2, x0, #0xff // use Aff0 as cpuid for now...
72 tst x0, x1 // check for cpuid==zero
73 b.ne 1f // secondary CPU
74
75 ldr x1, =GIC_DIST_BASE // GICD_CTLR
76 mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
77 str w0, [x1]
78
79
801: ldr x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0
81 // 128K for each redistributor, 256K strided...
82 mov x3, #1 << 18 // GICv4
83 mul x3, x3, x2
84 add x1, x1, x3
85 mov w0, #~0 // Grp1 interrupts
86 str w0, [x1], #4
87 b.ne 2f // Only local interrupts for secondary CPUs
88 ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
89 str w0, [x1], #4
90 str w0, [x1], #4
91 str w0, [x1], #4
92
|
93 /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
94 mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
95 orr x10, x10, #0xf // enable 0xf
96 msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
97 isb |
98
992: mov x0, #1
100 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
101 msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
102#else
103 tst x0, x1 // check for cpuid==zero
104 b.ne 1f // secondary CPU
105
106 ldr x1, =GIC_DIST_BASE // GICD_CTLR
107 mov w0, #3 // EnableGrp0 | EnableGrp1
108 str w0, [x1]
109
1101: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
111 mov w0, #~0 // Grp1 interrupts
112 str w0, [x1], #4
113 b.ne 2f // Only local interrupts for secondary CPUs
114 str w0, [x1], #4
115 str w0, [x1], #4
116
1172: ldr x1, =GIC_CPU_BASE // GICC_CTLR
118 ldr w0, [x1]
119 mov w0, #3 // EnableGrp0 | EnableGrp1
120 str w0, [x1]
121
122 mov w0, #1 << 7 // allow NS access to GICC_PMR
123 str w0, [x1, #4] // GICC_PMR
124#endif
125
126 msr sctlr_el2, xzr
127
128 /*
129 * Prepare the switch to the EL2_SP1 mode from EL3
130 */
131 ldr x0, =start_ns // Return after mode switch
132 mov x1, #0x3c9 // EL2_SP1 | D | A | I | F
133 msr elr_el3, x0
134 msr spsr_el3, x1
135 eret
136
137start_ns:
138 /*
139 * Kernel parameters
140 */
141 mov x0, xzr
142 mov x1, xzr
143 mov x2, xzr
144 mov x3, xzr
145
146 mrs x4, mpidr_el1
147 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
148 // Test the the MPIDR_EL1 register against 0xff00ffffff to
149 // extract the primary CPU.
150 ldr x1, =0xff00ffffff
151 tst x4, x1 // check for cpuid==zero
152 mov x1, xzr // load previous 'xzr' value back to x1
153 b.eq 2f // secondary CPU
154
155 /*
156 * Secondary CPUs
157 */
1581: wfe
159 ldr x4, =PHYS_OFFSET + 0xfff8
160 ldr x4, [x4]
161 cbz x4, 1b
162 br x4 // branch to the given address
163
1642:
165 /*
166 * UART initialisation (38400 8N1)
167 */
168 ldr x4, =UART_BASE // UART base
169 mov w5, #0x10 // ibrd
170 str w5, [x4, #0x24]
171 mov w5, #0xc300
172 orr w5, w5, #0x0001 // cr
173 str w5, [x4, #0x30]
174
175 /*
176 * CLCD output site MB
177 */
178 ldr x4, =SYSREGS_BASE
179 ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB
180 str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA
181 str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL
182
183 // set up the arch timer frequency
184 //ldr x0, =CNTFRQ
185 //msr cntfrq_el0, x0
186
187 /*
188 * Primary CPU
189 */
190 ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
191 ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
192 br x6
193
194 .ltorg
195
196 .org 0x200
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