1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
38
39 .text
40
41 .globl _start
42_start:
43 /*
44 * EL3 initialisation
45 */
46 mrs x0, CurrentEL
47 cmp x0, #0xc // EL3?
48 b.ne start_ns // skip EL3 initialisation
49
50 mov x0, #0x30 // RES1
51 orr x0, x0, #(1 << 0) // Non-secure EL1
52 orr x0, x0, #(1 << 8) // HVC enable
53 orr x0, x0, #(1 << 10) // 64-bit EL2
54 msr scr_el3, x0
55
56 msr cptr_el3, xzr // Disable copro. traps to EL3
57
58 ldr x0, =CNTFRQ
59 msr cntfrq_el0, x0
60
61 /*
62 * Check for the primary CPU to avoid a race on the distributor
63 * registers.
64 */
65 mrs x0, mpidr_el1
66 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
67 // Test the the MPIDR_EL1 register against 0xff00ffffff to
68 // extract the primary CPU.
69 ldr x1, =0xff00ffffff
70#ifdef GICV3
71 and x2, x0, #0xff // use Aff0 as cpuid for now...
72 tst x0, x1 // check for cpuid==zero
73 b.ne 1f // secondary CPU
74
75 ldr x1, =GIC_DIST_BASE // GICD_CTLR
76 mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
77 str w0, [x1]
78
79
801: ldr x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0
81 // 128K for each redistributor, 256K strided...
82 mov x3, #1 << 18 // GICv4
83 mul x3, x3, x2
84 add x1, x1, x3
85 mov w0, #~0 // Grp1 interrupts
86 str w0, [x1], #4
87 b.ne 2f // Only local interrupts for secondary CPUs
88 ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
89 str w0, [x1], #4
90 str w0, [x1], #4
91 str w0, [x1], #4
92
93
942: mov x0, #1
95 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
96 msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
97#else
98 tst x0, x1 // check for cpuid==zero
99 b.ne 1f // secondary CPU
100
101 ldr x1, =GIC_DIST_BASE // GICD_CTLR
102 mov w0, #3 // EnableGrp0 | EnableGrp1
103 str w0, [x1]
104
1051: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
106 mov w0, #~0 // Grp1 interrupts
107 str w0, [x1], #4
108 b.ne 2f // Only local interrupts for secondary CPUs
109 str w0, [x1], #4
110 str w0, [x1], #4
111
1122: ldr x1, =GIC_CPU_BASE // GICC_CTLR
113 ldr w0, [x1]
114 mov w0, #3 // EnableGrp0 | EnableGrp1
115 str w0, [x1]
116
117 mov w0, #1 << 7 // allow NS access to GICC_PMR
118 str w0, [x1, #4] // GICC_PMR
119#endif
120
121 msr sctlr_el2, xzr
122
123 /*
124 * Prepare the switch to the EL2_SP1 mode from EL3
125 */
126 ldr x0, =start_ns // Return after mode switch
127 mov x1, #0x3c9 // EL2_SP1 | D | A | I | F
128 msr elr_el3, x0
129 msr spsr_el3, x1
130 eret
131
132start_ns:
133 /*
134 * Kernel parameters
135 */
136 mov x0, xzr
137 mov x1, xzr
138 mov x2, xzr
139 mov x3, xzr
140
141 mrs x4, mpidr_el1
142 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
143 // Test the the MPIDR_EL1 register against 0xff00ffffff to
144 // extract the primary CPU.
145 ldr x1, =0xff00ffffff
146 tst x4, x1 // check for cpuid==zero
147 mov x1, xzr // load previous 'xzr' value back to x1
148 b.eq 2f // secondary CPU
149
150 /*
151 * Secondary CPUs
152 */
1531: wfe
154 ldr x4, =PHYS_OFFSET + 0xfff8
155 ldr x4, [x4]
156 cbz x4, 1b
157 br x4 // branch to the given address
158
1592:
160 /*
161 * UART initialisation (38400 8N1)
162 */
163 ldr x4, =UART_BASE // UART base
164 mov w5, #0x10 // ibrd
165 str w5, [x4, #0x24]
166 mov w5, #0xc300
167 orr w5, w5, #0x0001 // cr
168 str w5, [x4, #0x30]
169
170 /*
171 * CLCD output site MB
172 */
173 ldr x4, =SYSREGS_BASE
174 ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB
175 str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA
176 str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL
177
178 // set up the arch timer frequency
179 //ldr x0, =CNTFRQ
180 //msr cntfrq_el0, x0
181
182 /*
183 * Primary CPU
184 */
185 ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
186 ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
187 br x6
188
189 .ltorg
190
191 .org 0x200