| platform.S (8013:2dfcde2e9998) | platform.S (8017:2d68a6a11e44) |
|---|---|
| 1/* 2 * Copyright (c) 2003, 2004, 2005 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator, developed by Nathan Binkert, 7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew --- 299 unchanged lines hidden (view full) --- 308 ALIGN_BLOCK 309EXPORT(sys_wripir) 310 // 311 // Convert the processor number to a CPU mask 312 // 313 and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported 314 bis r31, 0x1, r16 // get a one 315 sll r16, r14, r14 // shift the bit to the right place | 1/* 2 * Copyright (c) 2003, 2004, 2005 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator, developed by Nathan Binkert, 7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew --- 299 unchanged lines hidden (view full) --- 308 ALIGN_BLOCK 309EXPORT(sys_wripir) 310 // 311 // Convert the processor number to a CPU mask 312 // 313 and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported 314 bis r31, 0x1, r16 // get a one 315 sll r16, r14, r14 // shift the bit to the right place |
| 316#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 317 sll r14,IPIQ_shift,r14 318#endif |
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| 316 | 319 |
| 320 |
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| 317 // 318 // Build the Broadcast Space base address 319 // | 321 // 322 // Build the Broadcast Space base address 323 // |
| 324#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 325 lda r16,0xf01(r31) 326 sll r16,32,r16 327 ldah r13,0xa0(r31) 328 sll r13,8,r13 329 bis r16,r13,r16 330 lda r16,IPIQ_addr(r16) 331#elif defined(TLASER) |
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| 320 lda r13, 0xff8e(r31) // Load the upper address bits 321 sll r13, 24, r13 // shift them to the top | 332 lda r13, 0xff8e(r31) // Load the upper address bits 333 sll r13, 24, r13 // shift them to the top |
| 334#endif |
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| 322 323 // 324 // Send out the IP Intr 325 // | 335 336 // 337 // Send out the IP Intr 338 // |
| 339#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 340 stq_p r14, 0(r16) // Tsunami MISC Register 341#elif defined(TLASER) |
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| 326 stq_p r14, 0x40(r13) // Write to TLIPINTR reg | 342 stq_p r14, 0x40(r13) // Write to TLIPINTR reg |
| 343#endif |
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| 327 wmb // Push out the store 328 hw_rei 329 330 331// cflush - PALcode for CFLUSH instruction 332// 333// SYS_CFLUSH 334// Entry: --- 2007 unchanged lines hidden --- | 344 wmb // Push out the store 345 hw_rei 346 347 348// cflush - PALcode for CFLUSH instruction 349// 350// SYS_CFLUSH 351// Entry: --- 2007 unchanged lines hidden --- |