1/* 2 * Copyright (c) 2003, 2004, 2005 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator, developed by Nathan Binkert, 7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew --- 1606 unchanged lines hidden (view full) --- 1615 1616 ALIGN_BLOCK 1617EXPORT(sys_machine_check) 1618 // Need to fill up the refill buffer (32 instructions) and 1619 // then flush the Icache again. 1620 // Also, due to possible 2nd Cbox register file write for 1621 // uncorrectable errors, no register file read or write for 7 cycles. 1622 |
1623 //nop 1624 .long 0x4000054 // call M5 Panic |
1625 mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites 1626 // r0 later 1627 nop 1628 nop 1629 1630 nop 1631 nop 1632 --- 80 unchanged lines hidden (view full) --- 1713 // r14 - base of Cbox IPRs in IO space 1714 // r0, r1, r4, r5, r6, r12, r13, r25 - available 1715 // r8, r9, r10 - available as all loads are physical 1716 // MCES<mchk> is set 1717 // 1718 // 1719 1720EXPORT(sys_mchk_collect_iprs) |
1721 .long 0x4000054 // call M5 Panic 1722 //mb // MB before reading Scache IPRs |
1723 mfpr r1, icperr_stat 1724 1725 mfpr r8, dcperr_stat 1726 mtpr r31, dc_flush // Flush the Dcache 1727 1728 mfpr r31, pt0 // Pad Mbox instructions from dc_flush 1729 mfpr r31, pt0 1730 nop --- 630 unchanged lines hidden --- |