| osfpal.S (8012:2f71125bf413) | osfpal.S (8013:2dfcde2e9998) |
|---|---|
| 1/* 2 * Copyright (c) 2003, 2004 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator, developed by Nathan Binkert, 7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew --- 16 unchanged lines hidden (view full) --- 25 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 26 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 27 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 28 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 29 * DAMAGES. 30 */ 31 32/* | 1/* 2 * Copyright (c) 2003, 2004 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator, developed by Nathan Binkert, 7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew --- 16 unchanged lines hidden (view full) --- 25 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 26 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 27 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 28 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 29 * DAMAGES. 30 */ 31 32/* |
| 33Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development Company, L.P. | 33 * Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development 34 * Company, L.P. 35 * 36 * Permission is hereby granted, free of charge, to any person 37 * obtaining a copy of this software and associated documentation 38 * files (the "Software"), to deal in the Software without 39 * restriction, including without limitation the rights to use, copy, 40 * modify, merge, publish, distribute, sublicense, and/or sell copies 41 * of the Software, and to permit persons to whom the Software is 42 * furnished to do so, subject to the following conditions: 43 * 44 * The above copyright notice and this permission notice shall be 45 * included in all copies or substantial portions of the Software. 46 * 47 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 50 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 51 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 52 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 53 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 54 * SOFTWARE. 55 */ |
| 34 | 56 |
| 35Permission is hereby granted, free of charge, to any person obtaining a copy of 36this software and associated documentation files (the "Software"), to deal in 37the Software without restriction, including without limitation the rights to 38use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 39of the Software, and to permit persons to whom the Software is furnished to do 40so, subject to the following conditions: 41 42The above copyright notice and this permission notice shall be included in all 43copies or substantial portions of the Software. 44 45THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 46IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 47FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 48AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 49LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 50OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 51SOFTWARE. 52*/ 53 | |
| 54// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl 55// since we don't have a mechanism to expand the data structures.... pb Nov/95 | 57// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl 58// since we don't have a mechanism to expand the data structures.... pb Nov/95 |
| 56 57// build_fixed_image: not sure what means 58// real_mm to be replaced during rewrite 59// remove_save_state remove_restore_state can be remooved to save space ?? 60 61 | |
| 62#include "ev5_defs.h" 63#include "ev5_impure.h" 64#include "ev5_alpha_defs.h" 65#include "ev5_paldef.h" 66#include "ev5_osfalpha_defs.h" 67#include "fromHudsonMacros.h" 68#include "fromHudsonOsf.h" 69#include "dc21164FromGasSources.h" 70 | 59#include "ev5_defs.h" 60#include "ev5_impure.h" 61#include "ev5_alpha_defs.h" 62#include "ev5_paldef.h" 63#include "ev5_osfalpha_defs.h" 64#include "fromHudsonMacros.h" 65#include "fromHudsonOsf.h" 66#include "dc21164FromGasSources.h" 67 |
| 71#ifdef SIMOS | |
| 72#define DEBUGSTORE(c) nop | 68#define DEBUGSTORE(c) nop |
| 73#else 74#define DEBUGSTORE(c) \ 75 lda r13, c(zero) ; \ 76 bsr r25, debugstore 77#endif | |
| 78 79#define DEBUG_EXC_ADDR()\ 80 bsr r25, put_exc_addr; \ 81 DEBUGSTORE(13) ; \ 82 DEBUGSTORE(10) 83 | 69 70#define DEBUG_EXC_ADDR()\ 71 bsr r25, put_exc_addr; \ 72 DEBUGSTORE(13) ; \ 73 DEBUGSTORE(10) 74 |
| 84#define egore 0 85#define acore 0 86#define beh_model 0 87#define ev5_p2 1 88#define ev5_p1 0 89#define ldvpte_bug_fix 1 90#define osf_chm_fix 0 91 92// Do we want to do this?? pb 93#define spe_fix 0 94// Do we want to do this?? pb 95#define build_fixed_image 0 96 97#define ev5_pass2 98#define enable_p4_fixups 0 99#define osf_svmin 1 100#define enable_physical_console 0 101#define fill_err_hack 0 102#define icflush_on_tbix 0 103#define max_cpuid 1 104#define perfmon_debug 0 105#define rawhide_system 0 106#define rax_mode 0 107 108 109// This is the fix for the user-mode super page references causing the machine to crash. 110#if (spe_fix == 1) && (build_fixed_image==1) 111#define hw_rei_spe br r31, hw_rei_update_spe 112#else | 75// This is the fix for the user-mode super page references causing the 76// machine to crash. |
| 113#define hw_rei_spe hw_rei | 77#define hw_rei_spe hw_rei |
| 114#endif | |
| 115 | 78 |
| 116 117// redefine a few of the distribution-code names to match the Hudson gas names. 118// opcodes 119#define ldqp ldq_p 120#define stqp stq_p 121#define ldlp ldl_p 122#define stlp stl_p 123 124#define r0 $0 125#define r1 $1 126#define r2 $2 127#define r3 $3 128#define r4 $4 129#define r5 $5 130#define r6 $6 131#define r7 $7 132#define r8 $8 133#define r9 $9 134#define r10 $10 135#define r11 $11 136#define r12 $12 137#define r13 $13 138#define r14 $14 139#define r15 $15 140#define r16 $16 141#define r17 $17 142#define r18 $18 143#define r19 $19 144#define r20 $20 145#define r21 $21 146#define r22 $22 147#define r23 $23 148#define r24 $24 149#define r25 $25 150#define r26 $26 151#define r27 $27 152#define r28 $28 153#define r29 $29 154#define r30 $30 155#define r31 $31 156 157// .title "EV5 OSF PAL" 158// .ident "V1.18" 159// 160//**************************************************************************** 161//* * 162//* Copyright (c) 1992, 1993, 1994, 1995 * 163//* by DIGITAL Equipment Corporation, Maynard, Mass. * 164//* * 165//* This software is furnished under a license and may be used and copied * 166//* only in accordance with the terms of such license and with the * 167//* inclusion of the above copyright notice. This software or any other * 168//* copies thereof may not be provided or otherwise made available to any * 169//* other person. No title to and ownership of the software is hereby * 170//* transferred. * 171//* * 172//* The information in this software is subject to change without notice * 173//* and should not be construed as a commitment by DIGITAL Equipment * 174//* Corporation. * 175//* * 176//* DIGITAL assumes no responsibility for the use or reliability of its * 177//* software on equipment which is not supplied by DIGITAL. * 178//* * 179//**************************************************************************** 180 181// .sbttl "Edit History" 182//+ 183// Who Rev When What 184// ------------ --- ----------- -------------------------------- 185// DB 0.0 03-Nov-1992 Start 186// DB 0.1 28-Dec-1992 add swpctx 187// DB 0.2 05-Jan-1993 Bug: PVC found mtpr dtb_CM -> virt ref bug 188// DB 0.3 11-Jan-1993 rearrange trap entry points 189// DB 0.4 01-Feb-1993 add tbi 190// DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal 191// DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14) 192// DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC 193// Bug: typo on register number for store in wrunique 194// Bug: rti to kern uses r16 as scratch 195// Bug: callsys saving wrong value in pt_usp 196// DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp 197// DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice 198// Bug: rti stl_c could corrupt the stack 199// Bug: unaligned returning wrong value in r17 (or should be and) 200// DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt 201// DB 0.11 23-Feb-1993 Turn caches on in reset flow 202// DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow 203// DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses 204// DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS 205// DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES 206// DB 0.16 12-May-1993 Update reset 207// New restriction: no mfpr exc_addr in cycle 1 of call_pal flows 208// Bug: in wrmces, not clearing DPC, DSC 209// Update swppal 210// Add pal bugchecks, pal_save_state, pal_restore_state 211// DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps. 212// New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn 213// DB 0.18 26-May-1993 PVC fixes 214// JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores 215// JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl 216// Bug: exc_addr was being loaded before stores that could dtb_miss in the following 217// routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN 218// JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines: 219// TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN:: 220// dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler: 221// osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN:: 222// Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles 223// JM 0.22 28-jul-1993 Add WRIPIR instruction 224// JM 0.23 05-aug-1993 Bump version number for release 225// JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation 226// JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals; 227// New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode), 228// and SWPCTX 229// JM 0.26 07-oct-1993 Re-implement pal_version 230// JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM 231// JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush 232// JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead 233// of mm_stat<opcode>. mm_stat contains original opcode, not hw_ld. 234// JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys 235// JM 0.31 15-nov-1993 BUG: WRFEN trashing r0 236// JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0 237// JM 0.33 24-nov-1993 save/restore_state - 238// BUG: use ivptbr to restore mvptbr 239// BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit 240// CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors 241// JM 0.34 20-dec-1993 BUG: set r11<mode> to kernel for ksnv halt case 242// BUG: generate ksnv halt when tb miss on kernel stack accesses 243// save exc_addr in r14 for invalid_dpte stack builder 244// JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in 245// the same shadow 246// JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS 247// New palcode restiction: mt icsr<fpe,hwe> --> 3 bubbles to hw_rei --affects wrfen 248// JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions 249// Hide impure area manipulations in macros 250// BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st 251// Add some pvc_violate statements 252// JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality; 253// Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments 254// Add code to ensure fen bit set in icsr before ldt 255// conditionally compile rax_more_reset out. 256// move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here 257// move rax reset stuff to ev5_osf_system_pal.m64 258// JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow 259// and performance monitoring bits 260// Change to save_state routine to save more iprs. 261// JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in 262// JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems) 263// remove_save_state,remove_restore_state;fix new pvc violation in save_state 264// JM 0.42 22-feb-1994 BUG: save_state overwriting r3 265// JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr 266// JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions 267// JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem) 268// New pal restriction in pal_restore_state: icsr<fpe>->floating instr = 3 bubbles 269// Add exc_sum and exc_mask to pal_save_state (not restore) 270// JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure 271// area. 272// Add performance counter support to swpctx and wrperfmon 273// JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix) 274// JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts 275// JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is 276// taken in the interrupt flow, stack is pushed twice. 277// SWPPAL - update to support ECO 59 to allow 0 as a valid address 278// Add itb flush to save/restore state routines 279// Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but 280// conforms to itbia restriction. 281// Added enable_physical_console flag (for enter/exit console routines only) 282// JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a 283// load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and 284// nmiss_fetch_err to nmiss_fetch_ldr31_err. 285// JM 1.00 1-aug-1994 Add pass2 support (swpctx) 286// JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2 287// JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2) 288// Moved perfmon code here from system file. 289// BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1) 290// JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit. 291// JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change 292// after ISR read, but we won't catch the ISR update. reverse order 293// JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31 294// JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code) 295// JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to 296// DTBMISS_SINGLE if not in palmode. 297// JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame 298// JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox 299// superpage mode in User mode and re-enable in kernel mode. 300// EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this. 301// JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2 302// ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid 303// cpu bug. 304// JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state 305// ES 1.13 17-mar-1995 Refine osf_chm_fix 306// ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix 307// ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state 308// Force pvc checking of exit_console 309// ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0 310// ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting) 311// instead of xor to maintain previous mode in pt_misc 312// ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does 313// not have pme set. The bits in icsr maintain the master enable state. 314// In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable 315// | |
| 316#define vmaj 1 317#define vmin 18 318#define vms_pal 1 319#define osf_pal 2 320#define pal_type osf_pal 321#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0)) | 79#define vmaj 1 80#define vmin 18 81#define vms_pal 1 82#define osf_pal 2 83#define pal_type osf_pal 84#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0)) |
| 322//- | |
| 323 | 85 |
| 324// .sbttl "PALtemp register usage" | |
| 325 | 86 |
| 326//+ | 87/////////////////////////// 88// PALtemp register usage 89/////////////////////////// 90 |
| 327// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage 328// for these PALtemps: 329// 330// pt0 local scratch 331// pt1 local scratch 332// pt2 entUna pt_entUna 333// pt3 CPU specific impure area pointer pt_impure 334// pt4 memory management temp 335// pt5 memory management temp 336// pt6 memory management temp 337// pt7 entIF pt_entIF 338// pt8 intmask pt_intmask 339// pt9 entSys pt_entSys 340// pt10 341// pt11 entInt pt_entInt 342// pt12 entArith pt_entArith 343// pt13 reserved for system specific PAL 344// pt14 reserved for system specific PAL 345// pt15 reserved for system specific PAL | 91// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage 92// for these PALtemps: 93// 94// pt0 local scratch 95// pt1 local scratch 96// pt2 entUna pt_entUna 97// pt3 CPU specific impure area pointer pt_impure 98// pt4 memory management temp 99// pt5 memory management temp 100// pt6 memory management temp 101// pt7 entIF pt_entIF 102// pt8 intmask pt_intmask 103// pt9 entSys pt_entSys 104// pt10 105// pt11 entInt pt_entInt 106// pt12 entArith pt_entArith 107// pt13 reserved for system specific PAL 108// pt14 reserved for system specific PAL 109// pt15 reserved for system specific PAL |
| 346// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces | 110// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, 111// pt_mces |
| 347// pt17 sysval pt_sysval 348// pt18 usp pt_usp 349// pt19 ksp pt_ksp 350// pt20 PTBR pt_ptbr 351// pt21 entMM pt_entMM 352// pt22 kgp pt_kgp 353// pt23 PCBB pt_pcbb 354// | 112// pt17 sysval pt_sysval 113// pt18 usp pt_usp 114// pt19 ksp pt_ksp 115// pt20 PTBR pt_ptbr 116// pt21 entMM pt_entMM 117// pt22 kgp pt_kgp 118// pt23 PCBB pt_pcbb 119// |
| 355//- | 120// |
| 356 | 121 |
| 357// .sbttl "PALshadow register usage" | 122 123///////////////////////////// 124// PALshadow register usage 125///////////////////////////// 126 |
| 358// | 127// |
| 359//+ 360// | |
| 361// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1. 362// This maps the OSF PAL usage of R8 - R14 and R25: 363// 364// r8 ITBmiss/DTBmiss scratch 365// r9 ITBmiss/DTBmiss scratch 366// r10 ITBmiss/DTBmiss scratch 367// r11 PS 368// r12 local scratch 369// r13 local scratch 370// r14 local scratch 371// r25 local scratch 372// | 128// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1. 129// This maps the OSF PAL usage of R8 - R14 and R25: 130// 131// r8 ITBmiss/DTBmiss scratch 132// r9 ITBmiss/DTBmiss scratch 133// r10 ITBmiss/DTBmiss scratch 134// r11 PS 135// r12 local scratch 136// r13 local scratch 137// r14 local scratch 138// r25 local scratch 139// |
| 373// 374//- | |
| 375 | 140 |
| 376// .sbttl "ALPHA symbol definitions" 377// _OSF_PSDEF GLOBAL 378// _OSF_PTEDEF GLOBAL 379// _OSF_VADEF GLOBAL 380// _OSF_PCBDEF GLOBAL 381// _OSF_SFDEF GLOBAL 382// _OSF_MMCSR_DEF GLOBAL 383// _SCBDEF GLOBAL 384// _FRMDEF GLOBAL 385// _EXSDEF GLOBAL 386// _OSF_A0_DEF GLOBAL 387// _MCESDEF GLOBAL | |
| 388 | 141 |
| 389// .sbttl "EV5 symbol definitions" | |
| 390 | 142 |
| 391// _EV5DEF 392// _PALTEMP 393// _MM_STAT_DEF 394// _EV5_MM 395// _EV5_IPLDEF 396 397// _HALT_CODES GLOBAL 398// _MCHK_CODES GLOBAL 399 400// _PAL_IMPURE 401// _PAL_LOGOUT 402 403 404 405 | |
| 406// .sbttl "PALcode configuration options" 407 408// There are a number of options that may be assembled into this version of 409// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit 410// the following). The options that can be adjusted cause the resultant PALcode 411// to reflect the desired target system. 412 | 143// .sbttl "PALcode configuration options" 144 145// There are a number of options that may be assembled into this version of 146// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit 147// the following). The options that can be adjusted cause the resultant PALcode 148// to reflect the desired target system. 149 |
| 413 414#define osfpal 1 // This is the PALcode for OSF. 415 416#ifndef rawhide_system 417 418#define rawhide_system 0 419#endif 420 421 422#ifndef real_mm 423// Page table translation vs 1-1 mapping 424#define real_mm 1 425#endif 426 427 428#ifndef rax_mode 429 430#define rax_mode 0 431#endif 432 433#ifndef egore 434// End of reset flow starts a program at 200000(hex). 435#define egore 1 436#endif 437 438#ifndef acore 439// End of reset flow starts a program at 40000(hex). 440#define acore 0 441#endif 442 443 444// assume acore+egore+rax_mode lt 2 // Assertion checker 445 446#ifndef beh_model 447// EV5 behavioral model specific code 448#define beh_model 1 449#endif 450 451#ifndef init_cbox 452// Reset flow init of Bcache and Scache 453#define init_cbox 1 454#endif 455 456#ifndef disable_crd 457// Decides whether the reset flow will disable 458#define disable_crd 0 459#endif 460 461 // correctable read interrupts via ICSR 462#ifndef perfmon_debug 463#define perfmon_debug 0 464#endif 465 466#ifndef icflush_on_tbix 467#define icflush_on_tbix 0 468#endif 469 470#ifndef remove_restore_state 471#define remove_restore_state 0 472#endif 473 474#ifndef remove_save_state 475#define remove_save_state 0 476#endif 477 478#ifndef enable_physical_console 479#define enable_physical_console 0 480#endif 481 482#ifndef ev5_p1 483#define ev5_p1 0 484#endif 485 486#ifndef ev5_p2 487#define ev5_p2 1 488#endif 489 490// assume ev5_p1+ev5_p2 eq 1 491 492#ifndef ldvpte_bug_fix 493#define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow. 494#endif 495 496#ifndef spe_fix 497// If set, disable super-page mode in user mode and re-enable 498#define spe_fix 0 499#endif 500 // in kernel. Workaround for cpu bug. 501#ifndef build_fixed_image 502#define build_fixed_image 0 503#endif 504 505 506#ifndef fill_err_hack 507// If set, disable fill_error mode in user mode and re-enable 508#define fill_err_hack 0 509#endif 510 511 // in kernel. Workaround for cpu bug. 512 513// .macro hw_rei_spe 514// .iif eq spe_fix, hw_rei 515//#if spe_fix != 0 516// 517// 518//#define hw_rei_chm_count hw_rei_chm_count + 1 519// p4_fixup_label \hw_rei_chm_count 520// .iif eq build_fixed_image, br r31, hw_rei_update_spe 521// .iif ne build_fixed_image, hw_rei 522//#endif 523// 524// .endm 525 526// Add flag "osf_chm_fix" to enable dcache in user mode only 527// to avoid cpu bug. 528 529#ifndef osf_chm_fix 530// If set, enable D-Cache in 531#define osf_chm_fix 0 532#endif 533 534#if osf_chm_fix != 0 535// user mode only. 536#define hw_rei_chm_count 0 537#endif 538 539#if osf_chm_fix != 0 540 541#define hw_rei_stall_chm_count 0 542#endif 543 544#ifndef enable_p4_fixups 545 546#define enable_p4_fixups 0 547#endif 548 549 // If set, do EV5 Pass 4 fixups 550#if spe_fix == 0 551 552#define osf_chm_fix 0 553#endif 554 555#if spe_fix == 0 556 557#define enable_p4_fixups 0 558#endif 559 560 // Only allow fixups if fix enabled 561 562 //Turn off fill_errors and MEM_NEM in user mode 563// .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_ 564// //save r22,r23,r24 565// stqp r22, 0x150(r31) //add 566// stqp r23, 0x158(r31) //contents 567// stqp r24, 0x160(r31) //bit mask 568// 569// lda r22, 0x82(r31) 570// ldah r22, 0x8740(r22) 571// sll r22, 8, r22 572// ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK 573// bis r23,r31,r23 574// 575// lda r24, 0x8(r31) // r24 <- MEM_NEM bit 576// beq r10, L10_ // IF user mode (r10<0> == 0) pal mode 577// bic r23, r24, r23 // set fillerr_en bit 578// br r31, L20_ // ELSE 579//L10_: bis r23, r24, r23 // clear fillerr_en bit 580//L20_: // ENDIF 581// 582// stlp r23, 0x80(r22) // write back the CIA_MASK register 583// mb 584// ldlp r23, 0x80(r22) 585// bis r23,r31,r23 586// mb 587// 588// lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL 589// ldah r22, 0x8740(r22) 590// sll r22, 8, r22 591// ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL 592// bis r23,r31,r23 593// 594// 595// lda r24, 0x400(r31) // r9 <- fillerr_en bit 596// beq r10, L30_ // IF user mode (r10<0> == 0) pal mode 597// bic r23, r24, r23 // set fillerr_en bit 598// br r31, L40_ // ELSE 599//L30_: bis r23, r24, r23 // clear fillerr_en bit 600//L40_: // ENDIF 601// 602// stlp r23, 0(r22) // write back the CIA_CTRL register 603// mb 604// ldlp r23, 0(r22) 605// bis r23,r31,r23 606// mb 607// 608// //restore r22,r23,r24 609// ldqp r22, 0x150(r31) 610// ldqp r23, 0x158(r31) 611// ldqp r24, 0x160(r31) 612// 613// .endm 614 | |
| 615// multiprocessor support can be enabled for a max of n processors by 616// setting the following to the number of processors on the system. 617// Note that this is really the max cpuid. 618 | 150// multiprocessor support can be enabled for a max of n processors by 151// setting the following to the number of processors on the system. 152// Note that this is really the max cpuid. 153 |
| 154#define max_cpuid 1 |
|
| 619#ifndef max_cpuid 620#define max_cpuid 8 621#endif 622 | 155#ifndef max_cpuid 156#define max_cpuid 8 157#endif 158 |
| 623#ifndef osf_svmin // platform specific palcode version number 624#define osf_svmin 0 625#endif 626 627 | 159#define osf_svmin 1 |
| 628#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0)) 629 | 160#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0)) 161 |
| 630// .mcall ldqp // override macro64 definition with macro from library 631// .mcall stqp // override macro64 definition with macro from library 632 633 634// .psect _pal,mix 635// huh pb pal_base: 636// huh pb #define current_block_base . - pal_base 637 638// .sbttl "RESET - Reset Trap Entry Point" 639//+ | 162// 163// RESET - Reset Trap Entry Point 164// |
| 640// RESET - offset 0000 641// Entry: 642// Vectored into via hardware trap on reset, or branched to 643// on swppal. 644// 645// r0 = whami 646// r1 = pal_base 647// r2 = base of scratch area 648// r3 = halt code 649// 650// 651// Function: 652// | 165// RESET - offset 0000 166// Entry: 167// Vectored into via hardware trap on reset, or branched to 168// on swppal. 169// 170// r0 = whami 171// r1 = pal_base 172// r2 = base of scratch area 173// r3 = halt code 174// 175// 176// Function: 177// |
| 653//- | 178// |
| 654 655 .text 0 656 . = 0x0000 | 179 180 .text 0 181 . = 0x0000 |
| 182 .globl _start |
|
| 657 .globl Pal_Base | 183 .globl Pal_Base |
| 184_start: |
|
| 658Pal_Base: 659 HDW_VECTOR(PAL_RESET_ENTRY) 660Trap_Reset: 661 nop | 185Pal_Base: 186 HDW_VECTOR(PAL_RESET_ENTRY) 187Trap_Reset: 188 nop |
| 662#ifdef SIMOS | |
| 663 /* 664 * store into r1 665 */ 666 br r1,sys_reset | 189 /* 190 * store into r1 191 */ 192 br r1,sys_reset |
| 667#else 668 /* following is a srcmax change */ | |
| 669 | 193 |
| 670 DEBUGSTORE(0x41) 671 /* The original code jumped using r1 as a linkage register to pass the base 672 of PALcode to the platform specific code. We use r1 to pass a parameter 673 from the SROM, so we hardcode the address of Pal_Base in platform.s 674 */ 675 br r31, sys_reset 676#endif 677 | |
| 678 // Specify PAL version info as a constant 679 // at a known location (reset + 8). 680 681 .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0> 682 .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0> 683 .long 0 684 .long 0 685pal_impure_start: 686 .quad 0 687pal_debug_ptr: 688 .quad 0 // reserved for debug pointer ; 20 | 194 // Specify PAL version info as a constant 195 // at a known location (reset + 8). 196 197 .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0> 198 .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0> 199 .long 0 200 .long 0 201pal_impure_start: 202 .quad 0 203pal_debug_ptr: 204 .quad 0 // reserved for debug pointer ; 20 |
| 689#if beh_model == 0 | |
| 690 691 | 205 206 |
| 692#if enable_p4_fixups != 0 693 694 695 .quad 0 696 .long p4_fixup_hw_rei_fixup_table 697#endif 698 699#else 700 701 .quad 0 // 702 .quad 0 //0x0030 703 .quad 0 704 .quad 0 //0x0040 705 .quad 0 706 .quad 0 //0x0050 707 .quad 0 708 .quad 0 //0x0060 709 .quad 0 710pal_enter_cns_address: 711 .quad 0 //0x0070 -- address to jump to from enter_console 712 .long <<sys_exit_console-pal_base>+1> //0x0078 -- offset to sys_exit_console (set palmode bit) 713#endif 714 715 716 717 718// .sbttl "IACCVIO- Istream Access Violation Trap Entry Point" 719 720//+ | 207// 208// IACCVIO - Istream Access Violation Trap Entry Point 209// |
| 721// IACCVIO - offset 0080 722// Entry: 723// Vectored into via hardware trap on Istream access violation or sign check error on PC. 724// 725// Function: 726// Build stack frame 727// a0 <- Faulting VA 728// a1 <- MMCSR (1 for ACV) 729// a2 <- -1 (for ifetch fault) 730// vector via entMM | 210// IACCVIO - offset 0080 211// Entry: 212// Vectored into via hardware trap on Istream access violation or sign check error on PC. 213// 214// Function: 215// Build stack frame 216// a0 <- Faulting VA 217// a1 <- MMCSR (1 for ACV) 218// a2 <- -1 (for ifetch fault) 219// vector via entMM |
| 731//- | 220// |
| 732 733 HDW_VECTOR(PAL_IACCVIO_ENTRY) 734Trap_Iaccvio: 735 DEBUGSTORE(0x42) 736 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 737 mtpr r31, ev5__ps // Set Ibox current mode to kernel 738 739 bis r11, r31, r12 // Save PS --- 29 unchanged lines hidden (view full) --- 769 mtpr r13, exc_addr // load exc_addr with entMM 770 // 1 cycle to hw_rei 771 mfpr r29, pt_kgp // get the kgp 772 773 subq r31, 1, r18 // pass flag of istream, as a2 774 hw_rei_spe 775 776 | 221 222 HDW_VECTOR(PAL_IACCVIO_ENTRY) 223Trap_Iaccvio: 224 DEBUGSTORE(0x42) 225 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 226 mtpr r31, ev5__ps // Set Ibox current mode to kernel 227 228 bis r11, r31, r12 // Save PS --- 29 unchanged lines hidden (view full) --- 258 mtpr r13, exc_addr // load exc_addr with entMM 259 // 1 cycle to hw_rei 260 mfpr r29, pt_kgp // get the kgp 261 262 subq r31, 1, r18 // pass flag of istream, as a2 263 hw_rei_spe 264 265 |
| 777// .sbttl "INTERRUPT- Interrupt Trap Entry Point" 778 779//+ | 266// 267// INTERRUPT - Interrupt Trap Entry Point 268// |
| 780// INTERRUPT - offset 0100 781// Entry: 782// Vectored into via trap on hardware interrupt 783// 784// Function: 785// check for halt interrupt 786// check for passive release (current ipl geq requestor) | 269// INTERRUPT - offset 0100 270// Entry: 271// Vectored into via trap on hardware interrupt 272// 273// Function: 274// check for halt interrupt 275// check for passive release (current ipl geq requestor) |
| 787// if necessary, switch to kernel mode 788// push stack frame, update ps (including current mode and ipl copies), sp, and gp | 276// if necessary, switch to kernel mode push stack frame, 277// update ps (including current mode and ipl copies), sp, and gp |
| 789// pass the interrupt info to the system module 790// | 278// pass the interrupt info to the system module 279// |
| 791//- 792 793 | 280// |
| 794 HDW_VECTOR(PAL_INTERRUPT_ENTRY) 795Trap_Interrupt: 796 mfpr r13, ev5__intid // Fetch level of interruptor 797 mfpr r25, ev5__isr // Fetch interrupt summary register 798 799 srl r25, isr_v_hlt, r9 // Get HLT bit 800 mfpr r14, ev5__ipl 801 --- 30 unchanged lines hidden (view full) --- 832 subq r13, 0x1d, r9 // Check for 1d, 1e, 1f 833 834 cmovge r9, r8, r12 // if .ge. 1d, then take shifted value 835 bis r12, r31, r11 // set new ps 836 837 mfpr r12, pt_intmask 838 and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already) 839 | 281 HDW_VECTOR(PAL_INTERRUPT_ENTRY) 282Trap_Interrupt: 283 mfpr r13, ev5__intid // Fetch level of interruptor 284 mfpr r25, ev5__isr // Fetch interrupt summary register 285 286 srl r25, isr_v_hlt, r9 // Get HLT bit 287 mfpr r14, ev5__ipl 288 --- 30 unchanged lines hidden (view full) --- 319 subq r13, 0x1d, r9 // Check for 1d, 1e, 1f 320 321 cmovge r9, r8, r12 // if .ge. 1d, then take shifted value 322 bis r12, r31, r11 // set new ps 323 324 mfpr r12, pt_intmask 325 and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already) 326 |
| 840#ifdef SIMOS | |
| 841 /* 842 * Lance had space problems. We don't. 843 */ 844 extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL 845 mfpr r29, pt_kgp // update gp 846 mtpr r14, ev5__ipl // load the new IPL into Ibox | 327 /* 328 * Lance had space problems. We don't. 329 */ 330 extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL 331 mfpr r29, pt_kgp // update gp 332 mtpr r14, ev5__ipl // load the new IPL into Ibox |
| 847#else 848// Moved the following three lines to sys_interrupt to make room for debug 849// extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL 850// mfpr r29, pt_kgp // update gp 851 852// mtpr r14, ev5__ipl // load the new IPL into Ibox 853#endif | |
| 854 br r31, sys_interrupt // Go handle interrupt 855 856 857 | 333 br r31, sys_interrupt // Go handle interrupt 334 335 336 |
| 858// .sbttl "ITBMISS- Istream TBmiss Trap Entry Point" 859 860//+ | 337// 338// ITBMISS - Istream TBmiss Trap Entry Point 339// |
| 861// ITBMISS - offset 0180 862// Entry: 863// Vectored into via hardware trap on Istream translation buffer miss. 864// 865// Function: 866// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid. 867// Can trap into DTBMISS_DOUBLE. 868// This routine can use the PALshadow registers r8, r9, and r10 869// | 340// ITBMISS - offset 0180 341// Entry: 342// Vectored into via hardware trap on Istream translation buffer miss. 343// 344// Function: 345// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid. 346// Can trap into DTBMISS_DOUBLE. 347// This routine can use the PALshadow registers r8, r9, and r10 348// |
| 870//- | 349// |
| 871 872 HDW_VECTOR(PAL_ITB_MISS_ENTRY) 873Trap_Itbmiss: | 350 351 HDW_VECTOR(PAL_ITB_MISS_ENTRY) 352Trap_Itbmiss: |
| 874#if real_mm == 0 875 876 877 // Simple 1-1 va->pa mapping 878 879 nop // Pad to align to E1 880 mfpr r8, exc_addr 881 882 srl r8, page_offset_size_bits, r9 883 sll r9, 32, r9 884 885 lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE 886 mtpr r9, itb_pte // E1 887 888 hw_rei_stall // Nital says I don't have to obey shadow wait rule here. 889#else 890 891 // Real MM mapping | 353 // Real MM mapping |
| 892 nop 893 mfpr r8, ev5__ifault_va_form // Get virtual address of PTE. 894 895 nop 896 mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss. 897 898pal_itb_ldq: 899 ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss --- 8 unchanged lines hidden (view full) --- 908 nop 909 bne r25, foe_ipte_handler // FOE is set 910 911 nop 912 mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB. 913 914 hw_rei_stall // 915 | 354 nop 355 mfpr r8, ev5__ifault_va_form // Get virtual address of PTE. 356 357 nop 358 mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss. 359 360pal_itb_ldq: 361 ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss --- 8 unchanged lines hidden (view full) --- 370 nop 371 bne r25, foe_ipte_handler // FOE is set 372 373 nop 374 mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB. 375 376 hw_rei_stall // 377 |
| 916#endif | |
| 917 | 378 |
| 918 919 920 921// .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point" 922 923//+ | 379// 380// DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point 381// |
| 924// DTBMISS_SINGLE - offset 0200 925// Entry: | 382// DTBMISS_SINGLE - offset 0200 383// Entry: |
| 926// Vectored into via hardware trap on Dstream single translation buffer miss. | 384// Vectored into via hardware trap on Dstream single translation 385// buffer miss. |
| 927// 928// Function: 929// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid. 930// Can trap into DTBMISS_DOUBLE. 931// This routine can use the PALshadow registers r8, r9, and r10 | 386// 387// Function: 388// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid. 389// Can trap into DTBMISS_DOUBLE. 390// This routine can use the PALshadow registers r8, r9, and r10 |
| 932//- | 391// |
| 933 934 HDW_VECTOR(PAL_DTB_MISS_ENTRY) 935Trap_Dtbmiss_Single: | 392 393 HDW_VECTOR(PAL_DTB_MISS_ENTRY) 394Trap_Dtbmiss_Single: |
| 936#if real_mm == 0 937 // Simple 1-1 va->pa mapping 938 mfpr r8, va // E0 939 srl r8, page_offset_size_bits, r9 940 941 sll r9, 32, r9 942 lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE 943 944 mtpr r9, dtb_pte // E0 945 nop // Pad to align to E0 946 947 948 949 mtpr r8, dtb_tag // E0 950 nop 951 952 nop // Pad tag write 953 nop 954 955 nop // Pad tag write 956 nop 957 958 hw_rei 959#else | |
| 960 mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0. 961 mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1. 962 963// DEBUGSTORE(0x45) 964// DEBUG_EXC_ADDR() 965 // Real MM mapping 966 mfpr r9, ev5__mm_stat // Get read/write bit. E0. 967 mtpr r10, pt6 // Stash exc_addr away --- 11 unchanged lines hidden (view full) --- 979 mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles. 980 mfpr r10, pt6 981 982 // Following 2 instructions take 2 cycles 983 mtpr r10, exc_addr // Return linkage in case we trapped. E1. 984 mfpr r31, pt0 // Pad the write to dtb_tag 985 986 hw_rei // Done, return | 395 mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0. 396 mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1. 397 398// DEBUGSTORE(0x45) 399// DEBUG_EXC_ADDR() 400 // Real MM mapping 401 mfpr r9, ev5__mm_stat // Get read/write bit. E0. 402 mtpr r10, pt6 // Stash exc_addr away --- 11 unchanged lines hidden (view full) --- 414 mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles. 415 mfpr r10, pt6 416 417 // Following 2 instructions take 2 cycles 418 mtpr r10, exc_addr // Return linkage in case we trapped. E1. 419 mfpr r31, pt0 // Pad the write to dtb_tag 420 421 hw_rei // Done, return |
| 987#endif | |
| 988 989 | 422 423 |
| 990 991 992// .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point" 993 994//+ | 424// 425// DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point 426// 427// |
| 995// DTBMISS_DOUBLE - offset 0280 996// Entry: | 428// DTBMISS_DOUBLE - offset 0280 429// Entry: |
| 997// Vectored into via hardware trap on Double TBmiss from single miss flows. | 430// Vectored into via hardware trap on Double TBmiss from single 431// miss flows. |
| 998// 999// r8 - faulting VA 1000// r9 - original MMstat 1001// r10 - original exc_addr (both itb,dtb miss) 1002// pt6 - original exc_addr (dtb miss flow only) 1003// VA IPR - locked with original faulting VA 1004// 1005// Function: 1006// Get PTE, if valid load TB and return. 1007// If not valid then take TNV/ACV exception. 1008// 1009// pt4 and pt5 are reserved for this flow. 1010// 1011// | 432// 433// r8 - faulting VA 434// r9 - original MMstat 435// r10 - original exc_addr (both itb,dtb miss) 436// pt6 - original exc_addr (dtb miss flow only) 437// VA IPR - locked with original faulting VA 438// 439// Function: 440// Get PTE, if valid load TB and return. 441// If not valid then take TNV/ACV exception. 442// 443// pt4 and pt5 are reserved for this flow. 444// 445// |
| 1012//- | 446// |
| 1013 1014 HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY) 1015Trap_Dtbmiss_double: | 447 448 HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY) 449Trap_Dtbmiss_double: |
| 1016#if ldvpte_bug_fix != 0 | |
| 1017 mtpr r8, pt4 // save r8 to do exc_addr check 1018 mfpr r8, exc_addr 1019 blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy! 1020 mfpr r8, pt4 // restore r8 | 450 mtpr r8, pt4 // save r8 to do exc_addr check 451 mfpr r8, exc_addr 452 blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy! 453 mfpr r8, pt4 // restore r8 |
| 1021#endif | |
| 1022 nop 1023 mtpr r22, pt5 // Get some scratch space. E1. 1024 // Due to virtual scheme, we can skip the first lookup and go 1025 // right to fetch of level 2 PTE 1026 sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA 1027 mtpr r21, pt4 // Get some scratch space. E1. 1028 1029 srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 1030 mfpr r21, pt_ptbr // Get physical address of the page table. 1031 1032 nop 1033 addq r21, r22, r21 // Index into page table for level 2 PTE. 1034 1035 sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA | 454 nop 455 mtpr r22, pt5 // Get some scratch space. E1. 456 // Due to virtual scheme, we can skip the first lookup and go 457 // right to fetch of level 2 PTE 458 sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA 459 mtpr r21, pt4 // Get some scratch space. E1. 460 461 srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 462 mfpr r21, pt_ptbr // Get physical address of the page table. 463 464 nop 465 addq r21, r22, r21 // Index into page table for level 2 PTE. 466 467 sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA |
| 1036 ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored) | 468 ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored) |
| 1037 1038 srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 1039 blbc r21, double_pte_inv // Check for Invalid PTE. 1040 1041 srl r21, 32, r21 // extract PFN from PTE 1042 sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8 1043 1044 addq r21, r22, r21 // Index into page table for level 3 PTE. 1045 nop 1046 | 469 470 srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 471 blbc r21, double_pte_inv // Check for Invalid PTE. 472 473 srl r21, 32, r21 // extract PFN from PTE 474 sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8 475 476 addq r21, r22, r21 // Index into page table for level 3 PTE. 477 nop 478 |
| 1047 ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored) | 479 ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored) |
| 1048 blbc r21, double_pte_inv // Check for invalid PTE. 1049 1050 mtpr r21, ev5__dtb_pte // Write the PTE. E0. 1051 mfpr r22, pt5 // Restore scratch register 1052 1053 mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles. 1054 mfpr r21, pt4 // Restore scratch register 1055 1056 nop // Pad write to tag. 1057 nop 1058 1059 nop // Pad write to tag. 1060 nop 1061 1062 hw_rei 1063 1064 1065 | 480 blbc r21, double_pte_inv // Check for invalid PTE. 481 482 mtpr r21, ev5__dtb_pte // Write the PTE. E0. 483 mfpr r22, pt5 // Restore scratch register 484 485 mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles. 486 mfpr r21, pt4 // Restore scratch register 487 488 nop // Pad write to tag. 489 nop 490 491 nop // Pad write to tag. 492 nop 493 494 hw_rei 495 496 497 |
| 1066// .sbttl "UNALIGN -- Dstream unalign trap" 1067//+ | 498// 499// UNALIGN -- Dstream unalign trap 500// |
| 1068// UNALIGN - offset 0300 1069// Entry: 1070// Vectored into via hardware trap on unaligned Dstream reference. 1071// 1072// Function: 1073// Build stack frame 1074// a0 <- Faulting VA 1075// a1 <- Opcode 1076// a2 <- src/dst register number 1077// vector via entUna | 501// UNALIGN - offset 0300 502// Entry: 503// Vectored into via hardware trap on unaligned Dstream reference. 504// 505// Function: 506// Build stack frame 507// a0 <- Faulting VA 508// a1 <- Opcode 509// a2 <- src/dst register number 510// vector via entUna |
| 1078//- | 511// |
| 1079 1080 HDW_VECTOR(PAL_UNALIGN_ENTRY) 1081Trap_Unalign: 1082/* DEBUGSTORE(0x47)*/ 1083 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1084 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1085 1086 mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss --- 43 unchanged lines hidden (view full) --- 1130 stq r14, osfsf_pc(sp) // save pc 1131 mfpr r25, pt_entuna // get entry point 1132 1133 1134 bis r12, r31, r11 // update ps 1135 br r31, unalign_trap_cont 1136 1137 | 512 513 HDW_VECTOR(PAL_UNALIGN_ENTRY) 514Trap_Unalign: 515/* DEBUGSTORE(0x47)*/ 516 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 517 mtpr r31, ev5__ps // Set Ibox current mode to kernel 518 519 mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss --- 43 unchanged lines hidden (view full) --- 563 stq r14, osfsf_pc(sp) // save pc 564 mfpr r25, pt_entuna // get entry point 565 566 567 bis r12, r31, r11 // update ps 568 br r31, unalign_trap_cont 569 570 |
| 1138 1139 1140// .sbttl "DFAULT - Dstream Fault Trap Entry Point" 1141 1142//+ | 571// 572// DFAULT - Dstream Fault Trap Entry Point 573// |
| 1143// DFAULT - offset 0380 1144// Entry: | 574// DFAULT - offset 0380 575// Entry: |
| 1145// Vectored into via hardware trap on dstream fault or sign check error on DVA. | 576// Vectored into via hardware trap on dstream fault or sign check 577// error on DVA. |
| 1146// 1147// Function: 1148// Ignore faults on FETCH/FETCH_M 1149// Check for DFAULT in PAL 1150// Build stack frame 1151// a0 <- Faulting VA 1152// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW) 1153// a2 <- R/W 1154// vector via entMM 1155// | 578// 579// Function: 580// Ignore faults on FETCH/FETCH_M 581// Check for DFAULT in PAL 582// Build stack frame 583// a0 <- Faulting VA 584// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW) 585// a2 <- R/W 586// vector via entMM 587// |
| 1156//- | 588// |
| 1157 HDW_VECTOR(PAL_D_FAULT_ENTRY) 1158Trap_Dfault: 1159// DEBUGSTORE(0x48) 1160 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1161 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1162 1163 mfpr r13, ev5__mm_stat // Get mmstat 1164 mfpr r8, exc_addr // get pc, preserve r14 --- 30 unchanged lines hidden (view full) --- 1195 1196 mtpr r30, pt_usp // save user stack 1197 bis r31, r31, r12 // Set new PS 1198 1199 mfpr r30, pt_ksp 1200 br r31, dfault_trap_cont 1201 1202 | 589 HDW_VECTOR(PAL_D_FAULT_ENTRY) 590Trap_Dfault: 591// DEBUGSTORE(0x48) 592 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 593 mtpr r31, ev5__ps // Set Ibox current mode to kernel 594 595 mfpr r13, ev5__mm_stat // Get mmstat 596 mfpr r8, exc_addr // get pc, preserve r14 --- 30 unchanged lines hidden (view full) --- 627 628 mtpr r30, pt_usp // save user stack 629 bis r31, r31, r12 // Set new PS 630 631 mfpr r30, pt_ksp 632 br r31, dfault_trap_cont 633 634 |
| 1203 1204 1205 1206// .sbttl "MCHK - Machine Check Trap Entry Point" 1207 1208//+ | 635// 636// MCHK - Machine Check Trap Entry Point 637// |
| 1209// MCHK - offset 0400 1210// Entry: 1211// Vectored into via hardware trap on machine check. 1212// 1213// Function: 1214// | 638// MCHK - offset 0400 639// Entry: 640// Vectored into via hardware trap on machine check. 641// 642// Function: 643// |
| 1215//- | 644// |
| 1216 1217 HDW_VECTOR(PAL_MCHK_ENTRY) 1218Trap_Mchk: 1219 DEBUGSTORE(0x49) 1220 mtpr r31, ic_flush_ctl // Flush the Icache 1221 br r31, sys_machine_check 1222 1223 | 645 646 HDW_VECTOR(PAL_MCHK_ENTRY) 647Trap_Mchk: 648 DEBUGSTORE(0x49) 649 mtpr r31, ic_flush_ctl // Flush the Icache 650 br r31, sys_machine_check 651 652 |
| 1224 1225 1226// .sbttl "OPCDEC - Illegal Opcode Trap Entry Point" 1227 1228//+ | 653// 654// OPCDEC - Illegal Opcode Trap Entry Point 655// |
| 1229// OPCDEC - offset 0480 1230// Entry: 1231// Vectored into via hardware trap on illegal opcode. 1232// 1233// Build stack frame 1234// a0 <- code 1235// a1 <- unpred 1236// a2 <- unpred 1237// vector via entIF 1238// | 656// OPCDEC - offset 0480 657// Entry: 658// Vectored into via hardware trap on illegal opcode. 659// 660// Build stack frame 661// a0 <- code 662// a1 <- unpred 663// a2 <- unpred 664// vector via entIF 665// |
| 1239//- | 666// |
| 1240 1241 HDW_VECTOR(PAL_OPCDEC_ENTRY) 1242Trap_Opcdec: 1243 DEBUGSTORE(0x4a) 1244//simos DEBUG_EXC_ADDR() 1245 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1246 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1247 --- 31 unchanged lines hidden (view full) --- 1279 mtpr r13, exc_addr // load exc_addr with entIF 1280 // 1 cycle to hw_rei, E1 1281 1282 mfpr r29, pt_kgp // get the kgp, E1 1283 1284 hw_rei_spe // done, E1 1285 1286 | 667 668 HDW_VECTOR(PAL_OPCDEC_ENTRY) 669Trap_Opcdec: 670 DEBUGSTORE(0x4a) 671//simos DEBUG_EXC_ADDR() 672 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 673 mtpr r31, ev5__ps // Set Ibox current mode to kernel 674 --- 31 unchanged lines hidden (view full) --- 706 mtpr r13, exc_addr // load exc_addr with entIF 707 // 1 cycle to hw_rei, E1 708 709 mfpr r29, pt_kgp // get the kgp, E1 710 711 hw_rei_spe // done, E1 712 713 |
| 1287 1288 1289 1290 1291// .sbttl "ARITH - Arithmetic Exception Trap Entry Point" 1292 1293//+ | 714// 715// ARITH - Arithmetic Exception Trap Entry Point 716// |
| 1294// ARITH - offset 0500 1295// Entry: 1296// Vectored into via hardware trap on arithmetic excpetion. 1297// 1298// Function: 1299// Build stack frame 1300// a0 <- exc_sum 1301// a1 <- exc_mask 1302// a2 <- unpred 1303// vector via entArith 1304// | 717// ARITH - offset 0500 718// Entry: 719// Vectored into via hardware trap on arithmetic excpetion. 720// 721// Function: 722// Build stack frame 723// a0 <- exc_sum 724// a1 <- exc_mask 725// a2 <- unpred 726// vector via entArith 727// |
| 1305//- | 728// |
| 1306 HDW_VECTOR(PAL_ARITH_ENTRY) 1307Trap_Arith: 1308 DEBUGSTORE(0x4b) 1309 and r11, osfps_m_mode, r12 // get mode bit 1310 mfpr r31, ev5__va // unlock mbox 1311 1312 bis r11, r31, r25 // save ps 1313 mfpr r14, exc_addr // get pc --- 22 unchanged lines hidden (view full) --- 1336 1337 stq r17, osfsf_a1(sp) 1338 mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle 1339 1340 stq r11, osfsf_ps(sp) // save ps 1341 bis r25, r31, r11 // set new ps 1342 1343 stq r16, osfsf_a0(sp) // save regs | 729 HDW_VECTOR(PAL_ARITH_ENTRY) 730Trap_Arith: 731 DEBUGSTORE(0x4b) 732 and r11, osfps_m_mode, r12 // get mode bit 733 mfpr r31, ev5__va // unlock mbox 734 735 bis r11, r31, r25 // save ps 736 mfpr r14, exc_addr // get pc --- 22 unchanged lines hidden (view full) --- 759 760 stq r17, osfsf_a1(sp) 761 mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle 762 763 stq r11, osfsf_ps(sp) // save ps 764 bis r25, r31, r11 // set new ps 765 766 stq r16, osfsf_a0(sp) // save regs |
| 1344 srl r13, exc_sum_v_swc, r16// shift data to correct position | 767 srl r13, exc_sum_v_swc, r16 // shift data to correct position |
| 1345 1346 stq r18, osfsf_a2(sp) 1347// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow 1348 mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask 1349 1350 stq r29, osfsf_gp(sp) 1351 mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1 1352 1353 mfpr r29, pt_kgp // get the kern gp - E1 1354 hw_rei_spe // done - E1 1355 1356 | 768 769 stq r18, osfsf_a2(sp) 770// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow 771 mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask 772 773 stq r29, osfsf_gp(sp) 774 mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1 775 776 mfpr r29, pt_kgp // get the kern gp - E1 777 hw_rei_spe // done - E1 778 779 |
| 1357 1358 1359 1360 1361// .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point" 1362 1363//+ | 780// 781// FEN - Illegal Floating Point Operation Trap Entry Point 782// |
| 1364// FEN - offset 0580 1365// Entry: 1366// Vectored into via hardware trap on illegal FP op. 1367// 1368// Function: 1369// Build stack frame 1370// a0 <- code 1371// a1 <- unpred 1372// a2 <- unpred 1373// vector via entIF 1374// | 783// FEN - offset 0580 784// Entry: 785// Vectored into via hardware trap on illegal FP op. 786// 787// Function: 788// Build stack frame 789// a0 <- code 790// a1 <- unpred 791// a2 <- unpred 792// vector via entIF 793// |
| 1375//- | 794// |
| 1376 1377 HDW_VECTOR(PAL_FEN_ENTRY) 1378Trap_Fen: 1379 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1380 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1381 1382 mfpr r14, exc_addr // get pc 1383 blbs r14, pal_pal_bug_check // check opcdec in palmode --- 48 unchanged lines hidden (view full) --- 1432 mtpr r13, exc_addr // load exc_addr with entIF 1433 // 1 cycle to hw_rei 1434 1435 mfpr r29, pt_kgp // get the kgp 1436 hw_rei_spe // done 1437 1438 1439 | 795 796 HDW_VECTOR(PAL_FEN_ENTRY) 797Trap_Fen: 798 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 799 mtpr r31, ev5__ps // Set Ibox current mode to kernel 800 801 mfpr r14, exc_addr // get pc 802 blbs r14, pal_pal_bug_check // check opcdec in palmode --- 48 unchanged lines hidden (view full) --- 851 mtpr r13, exc_addr // load exc_addr with entIF 852 // 1 cycle to hw_rei 853 854 mfpr r29, pt_kgp // get the kgp 855 hw_rei_spe // done 856 857 858 |
| 1440// .sbttl "Misc handlers" 1441 // Start area for misc code. 1442//+ 1443//dfault_trap_cont | 859////////////////////////////////////////////////////////////////////////////// 860// Misc handlers - Start area for misc code. 861////////////////////////////////////////////////////////////////////////////// 862 863// 864// dfault_trap_cont |
| 1444// A dfault trap has been taken. The sp has been updated if necessary. 1445// Push a stack frame a vector via entMM. 1446// 1447// Current state: 1448// r12 - new PS 1449// r13 - MMstat 1450// VA - locked 1451// | 865// A dfault trap has been taken. The sp has been updated if necessary. 866// Push a stack frame a vector via entMM. 867// 868// Current state: 869// r12 - new PS 870// r13 - MMstat 871// VA - locked 872// |
| 1452//- | 873// |
| 1453 ALIGN_BLOCK 1454dfault_trap_cont: 1455 lda sp, 0-osfsf_c_size(sp)// allocate stack space 1456 mfpr r25, ev5__va // Fetch VA/unlock 1457 1458 stq r18, osfsf_a2(sp) // a2 1459 and r13, 1, r18 // Clean r/w bit for a2 1460 --- 13 unchanged lines hidden (view full) --- 1474 cmovlbs r17, 1, r17 // a2. acv overrides fox. 1475 1476 mtpr r25, exc_addr // load exc_addr with entMM 1477 // 1 cycle to hw_rei 1478 mfpr r29, pt_kgp // get the kgp 1479 1480 hw_rei_spe // done 1481 | 874 ALIGN_BLOCK 875dfault_trap_cont: 876 lda sp, 0-osfsf_c_size(sp)// allocate stack space 877 mfpr r25, ev5__va // Fetch VA/unlock 878 879 stq r18, osfsf_a2(sp) // a2 880 and r13, 1, r18 // Clean r/w bit for a2 881 --- 13 unchanged lines hidden (view full) --- 895 cmovlbs r17, 1, r17 // a2. acv overrides fox. 896 897 mtpr r25, exc_addr // load exc_addr with entMM 898 // 1 cycle to hw_rei 899 mfpr r29, pt_kgp // get the kgp 900 901 hw_rei_spe // done 902 |
| 1482//+ | 903// |
| 1483//unalign_trap_cont 1484// An unalign trap has been taken. Just need to finish up a few things. 1485// 1486// Current state: 1487// r25 - entUna 1488// r13 - shifted MMstat 1489// | 904//unalign_trap_cont 905// An unalign trap has been taken. Just need to finish up a few things. 906// 907// Current state: 908// r25 - entUna 909// r13 - shifted MMstat 910// |
| 1490//- | 911// |
| 1491 ALIGN_BLOCK 1492unalign_trap_cont: 1493 mtpr r25, exc_addr // load exc_addr with entUna 1494 // 1 cycle to hw_rei 1495 1496 1497 mfpr r29, pt_kgp // get the kgp 1498 and r13, mm_stat_m_ra, r18 // Clean Ra for a2 1499 1500 hw_rei_spe // done 1501 1502 1503 | 912 ALIGN_BLOCK 913unalign_trap_cont: 914 mtpr r25, exc_addr // load exc_addr with entUna 915 // 1 cycle to hw_rei 916 917 918 mfpr r29, pt_kgp // get the kgp 919 and r13, mm_stat_m_ra, r18 // Clean Ra for a2 920 921 hw_rei_spe // done 922 923 924 |
| 1504//+ | 925// |
| 1505// dfault_in_pal 1506// Dfault trap was taken, exc_addr points to a PAL PC. 1507// r9 - mmstat<opcode> right justified 1508// r8 - exception address 1509// 1510// These are the cases: 1511// opcode was STQ -- from a stack builder, KSP not valid halt 1512// r14 - original exc_addr --- 5 unchanged lines hidden (view full) --- 1518// opcode was LDQ -- retsys or rti stack read, KSP not valid halt 1519// r11 - original PS 1520// r14 - original exc_addr 1521// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables 1522// r10 - original exc_addr 1523// r11 - original PS 1524// 1525// | 926// dfault_in_pal 927// Dfault trap was taken, exc_addr points to a PAL PC. 928// r9 - mmstat<opcode> right justified 929// r8 - exception address 930// 931// These are the cases: 932// opcode was STQ -- from a stack builder, KSP not valid halt 933// r14 - original exc_addr --- 5 unchanged lines hidden (view full) --- 939// opcode was LDQ -- retsys or rti stack read, KSP not valid halt 940// r11 - original PS 941// r14 - original exc_addr 942// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables 943// r10 - original exc_addr 944// r11 - original PS 945// 946// |
| 1526//- | 947// |
| 1527 ALIGN_BLOCK 1528dfault_in_pal: 1529 DEBUGSTORE(0x50) 1530 bic r8, 3, r8 // Clean PC 1531 mfpr r9, pal_base 1532 1533 mfpr r31, va // unlock VA | 948 ALIGN_BLOCK 949dfault_in_pal: 950 DEBUGSTORE(0x50) 951 bic r8, 3, r8 // Clean PC 952 mfpr r9, pal_base 953 954 mfpr r31, va // unlock VA |
| 1534#if real_mm != 0 1535 // if not real_mm, should never get here from miss flows | |
| 1536 | 955 |
| 956 // if not real_mm, should never get here from miss flows 957 |
|
| 1537 subq r9, r8, r8 // pal_base - offset 1538 1539 lda r9, pal_itb_ldq-pal_base(r8) 1540 nop 1541 1542 beq r9, dfault_do_bugcheck 1543 lda r9, pal_dtb_ldq-pal_base(r8) 1544 1545 beq r9, dfault_do_bugcheck | 958 subq r9, r8, r8 // pal_base - offset 959 960 lda r9, pal_itb_ldq-pal_base(r8) 961 nop 962 963 beq r9, dfault_do_bugcheck 964 lda r9, pal_dtb_ldq-pal_base(r8) 965 966 beq r9, dfault_do_bugcheck |
| 1546#endif | |
| 1547 1548// 1549// KSP invalid halt case -- 1550ksp_inval_halt: 1551 DEBUGSTORE(76) 1552 bic r11, osfps_m_mode, r11 // set ps to kernel mode 1553 mtpr r0, pt0 1554 1555 mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode 1556 mtpr r31, ips 1557 1558 mtpr r14, exc_addr // Set PC to instruction that caused trouble | 967 968// 969// KSP invalid halt case -- 970ksp_inval_halt: 971 DEBUGSTORE(76) 972 bic r11, osfps_m_mode, r11 // set ps to kernel mode 973 mtpr r0, pt0 974 975 mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode 976 mtpr r31, ips 977 978 mtpr r14, exc_addr // Set PC to instruction that caused trouble |
| 1559//orig pvc_jsr updpcb, bsr=1 | |
| 1560 bsr r0, pal_update_pcb // update the pcb 1561 1562 lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt 1563 br r31, sys_enter_console // enter the console 1564 1565 ALIGN_BRANCH 1566dfault_do_bugcheck: 1567 bis r10, r31, r14 // bugcheck expects exc_addr in r14 1568 br r31, pal_pal_bug_check 1569 1570 | 979 bsr r0, pal_update_pcb // update the pcb 980 981 lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt 982 br r31, sys_enter_console // enter the console 983 984 ALIGN_BRANCH 985dfault_do_bugcheck: 986 bis r10, r31, r14 // bugcheck expects exc_addr in r14 987 br r31, pal_pal_bug_check 988 989 |
| 1571 ALIGN_BLOCK 1572//+ | 990// |
| 1573// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31 1574// On entry - 1575// r14 - exc_addr 1576// VA is locked 1577// | 991// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31 992// On entry - 993// r14 - exc_addr 994// VA is locked 995// |
| 1578//- | 996// 997 ALIGN_BLOCK |
| 1579dfault_fetch_ldr31_err: 1580 mtpr r11, ev5__dtb_cm 1581 mtpr r11, ev5__ps // Make sure ps hasn't changed 1582 1583 mfpr r31, va // unlock the mbox 1584 addq r14, 4, r14 // inc the pc to skip the fetch 1585 1586 mtpr r14, exc_addr // give ibox new PC 1587 mfpr r31, pt0 // pad exc_addr write 1588 1589 hw_rei 1590 1591 1592 1593 ALIGN_BLOCK | 998dfault_fetch_ldr31_err: 999 mtpr r11, ev5__dtb_cm 1000 mtpr r11, ev5__ps // Make sure ps hasn't changed 1001 1002 mfpr r31, va // unlock the mbox 1003 addq r14, 4, r14 // inc the pc to skip the fetch 1004 1005 mtpr r14, exc_addr // give ibox new PC 1006 mfpr r31, pt0 // pad exc_addr write 1007 1008 hw_rei 1009 1010 1011 1012 ALIGN_BLOCK |
| 1594//+ | 1013// |
| 1595// sys_from_kern 1596// callsys from kernel mode - OS bugcheck machine check 1597// | 1014// sys_from_kern 1015// callsys from kernel mode - OS bugcheck machine check 1016// |
| 1598//- | 1017// |
| 1599sys_from_kern: 1600 mfpr r14, exc_addr // PC points to call_pal 1601 subq r14, 4, r14 1602 1603 lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code 1604 br r31, pal_pal_mchk 1605 1606 | 1018sys_from_kern: 1019 mfpr r14, exc_addr // PC points to call_pal 1020 subq r14, 4, r14 1021 1022 lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code 1023 br r31, pal_pal_mchk 1024 1025 |
| 1607// .sbttl "Continuation of long call_pal flows" 1608 ALIGN_BLOCK 1609//+ | 1026// Continuation of long call_pal flows 1027// |
| 1610// wrent_tbl 1611// Table to write *int in paltemps. 1612// 4 instructions/entry 1613// r16 has new value 1614// | 1028// wrent_tbl 1029// Table to write *int in paltemps. 1030// 4 instructions/entry 1031// r16 has new value 1032// |
| 1615//- | 1033// 1034 ALIGN_BLOCK |
| 1616wrent_tbl: 1617//orig pvc_jsr wrent, dest=1 1618 nop 1619 mtpr r16, pt_entint 1620 1621 mfpr r31, pt0 // Pad for mt->mf paltemp rule 1622 hw_rei 1623 --- 33 unchanged lines hidden (view full) --- 1657//orig pvc_jsr wrent, dest=1 1658 nop 1659 mtpr r16, pt_entsys 1660 1661 mfpr r31, pt0 // Pad for mt->mf paltemp rule 1662 hw_rei 1663 1664 ALIGN_BLOCK | 1035wrent_tbl: 1036//orig pvc_jsr wrent, dest=1 1037 nop 1038 mtpr r16, pt_entint 1039 1040 mfpr r31, pt0 // Pad for mt->mf paltemp rule 1041 hw_rei 1042 --- 33 unchanged lines hidden (view full) --- 1076//orig pvc_jsr wrent, dest=1 1077 nop 1078 mtpr r16, pt_entsys 1079 1080 mfpr r31, pt0 // Pad for mt->mf paltemp rule 1081 hw_rei 1082 1083 ALIGN_BLOCK |
| 1665//+ | 1084// |
| 1666// tbi_tbl 1667// Table to do tbi instructions 1668// 4 instructions per entry | 1085// tbi_tbl 1086// Table to do tbi instructions 1087// 4 instructions per entry |
| 1669//- | 1088// |
| 1670tbi_tbl: 1671 // -2 tbia 1672//orig pvc_jsr tbi, dest=1 1673 mtpr r31, ev5__dtb_ia // Flush DTB 1674 mtpr r31, ev5__itb_ia // Flush ITB 1675 | 1089tbi_tbl: 1090 // -2 tbia 1091//orig pvc_jsr tbi, dest=1 1092 mtpr r31, ev5__dtb_ia // Flush DTB 1093 mtpr r31, ev5__itb_ia // Flush ITB 1094 |
| 1676#if icflush_on_tbix != 0 1677 1678 1679 br r31, pal_ic_flush // Flush Icache 1680#else 1681 | |
| 1682 hw_rei_stall | 1095 hw_rei_stall |
| 1683#endif | |
| 1684 1685 nop // Pad table 1686 1687 // -1 tbiap 1688//orig pvc_jsr tbi, dest=1 1689 mtpr r31, ev5__dtb_iap // Flush DTB 1690 mtpr r31, ev5__itb_iap // Flush ITB 1691 | 1096 1097 nop // Pad table 1098 1099 // -1 tbiap 1100//orig pvc_jsr tbi, dest=1 1101 mtpr r31, ev5__dtb_iap // Flush DTB 1102 mtpr r31, ev5__itb_iap // Flush ITB 1103 |
| 1692#if icflush_on_tbix != 0 1693 1694 1695 br r31, pal_ic_flush // Flush Icache 1696#else 1697 | |
| 1698 hw_rei_stall | 1104 hw_rei_stall |
| 1699#endif | |
| 1700 1701 nop // Pad table 1702 1703 1704 // 0 unused 1705//orig pvc_jsr tbi, dest=1 1706 hw_rei // Pad table 1707 nop 1708 nop 1709 nop 1710 1711 1712 // 1 tbisi 1713//orig pvc_jsr tbi, dest=1 | 1105 1106 nop // Pad table 1107 1108 1109 // 0 unused 1110//orig pvc_jsr tbi, dest=1 1111 hw_rei // Pad table 1112 nop 1113 nop 1114 nop 1115 1116 1117 // 1 tbisi 1118//orig pvc_jsr tbi, dest=1 |
| 1714#if icflush_on_tbix != 0 | |
| 1715 | 1119 |
| 1716 1717 | |
| 1718 nop | 1120 nop |
| 1719 br r31, pal_ic_flush_and_tbisi // Flush Icache | |
| 1720 nop | 1121 nop |
| 1721 nop // Pad table 1722#else 1723 1724 nop 1725 nop | |
| 1726 mtpr r17, ev5__itb_is // Flush ITB 1727 hw_rei_stall | 1122 mtpr r17, ev5__itb_is // Flush ITB 1123 hw_rei_stall |
| 1728#endif | |
| 1729 | 1124 |
| 1730 1731 | |
| 1732 // 2 tbisd 1733//orig pvc_jsr tbi, dest=1 1734 mtpr r17, ev5__dtb_is // Flush DTB. 1735 nop 1736 1737 nop 1738 hw_rei_stall 1739 1740 1741 // 3 tbis 1742//orig pvc_jsr tbi, dest=1 1743 mtpr r17, ev5__dtb_is // Flush DTB | 1125 // 2 tbisd 1126//orig pvc_jsr tbi, dest=1 1127 mtpr r17, ev5__dtb_is // Flush DTB. 1128 nop 1129 1130 nop 1131 hw_rei_stall 1132 1133 1134 // 3 tbis 1135//orig pvc_jsr tbi, dest=1 1136 mtpr r17, ev5__dtb_is // Flush DTB |
| 1744#if icflush_on_tbix != 0 1745 1746 1747 br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB 1748#else | |
| 1749 br r31, tbi_finish 1750 ALIGN_BRANCH 1751tbi_finish: 1752 mtpr r17, ev5__itb_is // Flush ITB 1753 hw_rei_stall | 1137 br r31, tbi_finish 1138 ALIGN_BRANCH 1139tbi_finish: 1140 mtpr r17, ev5__itb_is // Flush ITB 1141 hw_rei_stall |
| 1754#endif | |
| 1755 1756 1757 1758 ALIGN_BLOCK | 1142 1143 1144 1145 ALIGN_BLOCK |
| 1759//+ | 1146// |
| 1760// bpt_bchk_common: 1761// Finish up the bpt/bchk instructions | 1147// bpt_bchk_common: 1148// Finish up the bpt/bchk instructions |
| 1762//- | 1149// |
| 1763bpt_bchk_common: 1764 stq r18, osfsf_a2(sp) // a2 1765 mfpr r13, pt_entif // get entry point 1766 1767 stq r12, osfsf_ps(sp) // save old ps 1768 stq r14, osfsf_pc(sp) // save pc 1769 1770 stq r29, osfsf_gp(sp) // save gp 1771 mtpr r13, exc_addr // load exc_addr with entIF 1772 // 1 cycle to hw_rei 1773 1774 mfpr r29, pt_kgp // get the kgp 1775 1776 1777 hw_rei_spe // done 1778 1779 1780 ALIGN_BLOCK | 1150bpt_bchk_common: 1151 stq r18, osfsf_a2(sp) // a2 1152 mfpr r13, pt_entif // get entry point 1153 1154 stq r12, osfsf_ps(sp) // save old ps 1155 stq r14, osfsf_pc(sp) // save pc 1156 1157 stq r29, osfsf_gp(sp) // save gp 1158 mtpr r13, exc_addr // load exc_addr with entIF 1159 // 1 cycle to hw_rei 1160 1161 mfpr r29, pt_kgp // get the kgp 1162 1163 1164 hw_rei_spe // done 1165 1166 1167 ALIGN_BLOCK |
| 1781//+ | 1168// |
| 1782// rti_to_user 1783// Finish up the rti instruction | 1169// rti_to_user 1170// Finish up the rti instruction |
| 1784//- | 1171// |
| 1785rti_to_user: 1786 mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 1787 mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 1788 1789 mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles 1790 mtpr r25, pt_ksp // save off incase RTI to user 1791 1792 mfpr r30, pt_usp 1793 hw_rei_spe // and back 1794 1795 1796 ALIGN_BLOCK | 1172rti_to_user: 1173 mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 1174 mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 1175 1176 mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles 1177 mtpr r25, pt_ksp // save off incase RTI to user 1178 1179 mfpr r30, pt_usp 1180 hw_rei_spe // and back 1181 1182 1183 ALIGN_BLOCK |
| 1797//+ | 1184// |
| 1798// rti_to_kern 1799// Finish up the rti instruction | 1185// rti_to_kern 1186// Finish up the rti instruction |
| 1800//- | 1187// |
| 1801rti_to_kern: 1802 and r12, osfps_m_ipl, r11 // clean ps 1803 mfpr r12, pt_intmask // get int mask 1804 1805 extbl r12, r11, r12 // get mask for this ipl 1806 mtpr r25, pt_ksp // save off incase RTI to user 1807 1808 mtpr r12, ev5__ipl // set the new ipl. 1809 or r25, r31, sp // sp 1810 1811// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals 1812 hw_rei 1813 1814 ALIGN_BLOCK | 1188rti_to_kern: 1189 and r12, osfps_m_ipl, r11 // clean ps 1190 mfpr r12, pt_intmask // get int mask 1191 1192 extbl r12, r11, r12 // get mask for this ipl 1193 mtpr r25, pt_ksp // save off incase RTI to user 1194 1195 mtpr r12, ev5__ipl // set the new ipl. 1196 or r25, r31, sp // sp 1197 1198// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals 1199 hw_rei 1200 1201 ALIGN_BLOCK |
| 1815//+ | 1202// |
| 1816// swpctx_cont 1817// Finish up the swpctx instruction | 1203// swpctx_cont 1204// Finish up the swpctx instruction |
| 1818//- | 1205// |
| 1819 1820swpctx_cont: | 1206 1207swpctx_cont: |
| 1821#if ev5_p1 != 0 | |
| 1822 | 1208 |
| 1823 1824 bic r25, r24, r25 // clean icsr<FPE> 1825 get_impure r8 // get impure pointer 1826 1827 sll r12, icsr_v_fpe, r12 // shift new fen to pos 1828 fix_impure_ipr r8 // adjust impure pointer 1829 1830 restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits 1831 srl r23, 32, r24 // move asn to low asn pos 1832 1833 ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr 1834 srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 1835 1836 or r25, r12, r25 // icsr with new fen 1837 sll r24, itb_asn_v_asn, r12 1838 1839#else 1840 | |
| 1841 bic r25, r24, r25 // clean icsr<FPE,PMP> 1842 sll r12, icsr_v_fpe, r12 // shift new fen to pos 1843 | 1209 bic r25, r24, r25 // clean icsr<FPE,PMP> 1210 sll r12, icsr_v_fpe, r12 // shift new fen to pos 1211 |
| 1844 ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr | 1212 ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr |
| 1845 srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 1846 1847 or r25, r12, r25 // icsr with new fen 1848 srl r23, 32, r24 // move asn to low asn pos 1849 1850 and r22, 1, r22 1851 sll r24, itb_asn_v_asn, r12 1852 1853 sll r22, icsr_v_pmp, r22 1854 nop 1855 1856 or r25, r22, r25 // icsr with new pme | 1213 srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 1214 1215 or r25, r12, r25 // icsr with new fen 1216 srl r23, 32, r24 // move asn to low asn pos 1217 1218 and r22, 1, r22 1219 sll r24, itb_asn_v_asn, r12 1220 1221 sll r22, icsr_v_pmp, r22 1222 nop 1223 1224 or r25, r22, r25 // icsr with new pme |
| 1857#endif | |
| 1858 1859 sll r24, dtb_asn_v_asn, r24 1860 1861 subl r23, r13, r13 // gen new cc offset 1862 mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4 1863 1864 mtpr r24, dtb_asn // Load up new ASN 1865 mtpr r25, icsr // write the icsr 1866 1867 sll r14, page_offset_size_bits, r14 // Move PTBR into internal position. | 1225 1226 sll r24, dtb_asn_v_asn, r24 1227 1228 subl r23, r13, r13 // gen new cc offset 1229 mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4 1230 1231 mtpr r24, dtb_asn // Load up new ASN 1232 mtpr r25, icsr // write the icsr 1233 1234 sll r14, page_offset_size_bits, r14 // Move PTBR into internal position. |
| 1868 ldqp r25, osfpcb_q_usp(r16) // get new usp | 1235 ldq_p r25, osfpcb_q_usp(r16) // get new usp |
| 1869 1870 insll r13, 4, r13 // >> 32 | 1236 1237 insll r13, 4, r13 // >> 32 |
| 1871// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow | 1238// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow |
| 1872 mtpr r14, pt_ptbr // load the new ptbr 1873 1874 mtpr r13, cc // set new offset | 1239 mtpr r14, pt_ptbr // load the new ptbr 1240 1241 mtpr r13, cc // set new offset |
| 1875 ldqp r30, osfpcb_q_ksp(r16) // get new ksp | 1242 ldq_p r30, osfpcb_q_ksp(r16) // get new ksp |
| 1876 | 1243 |
| 1877// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow | 1244// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow |
| 1878 mtpr r25, pt_usp // save usp 1879 | 1245 mtpr r25, pt_usp // save usp 1246 |
| 1880#if ev5_p1 != 0 1881 1882 1883 blbc r8, no_pm_change // if monitoring all processes -- no need to change pm 1884 1885 // otherwise, monitoring select processes - update pm 1886 lda r25, 0x3F(r31) 1887 cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings 1888 1889 sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask 1890 mfpr r22, ev5__pmctr 1891 1892 and r8, r25, r8 // mask new ctl value 1893 bic r22, r25, r22 // clear ctl field in pmctr 1894 1895 or r8, r22, r8 1896 mtpr r8, ev5__pmctr 1897 1898no_pm_change: 1899#endif 1900 1901 1902#if osf_chm_fix != 0 1903 1904 1905 p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here 1906 1907#if build_fixed_image != 0 1908 1909 1910 hw_rei_stall 1911#else 1912 1913 mfpr r9, pt_pcbb // get FEN 1914#endif 1915 1916 ldqp r9, osfpcb_q_fen(r9) 1917 blbc r9, no_pm_change_10_ // skip if FEN disabled 1918 1919 mb // ensure no outstanding fills 1920 lda r12, 1<<dc_mode_v_dc_ena(r31) 1921 mtpr r12, dc_mode // turn dcache on so we can flush it 1922 nop // force correct slotting 1923 mfpr r31, pt0 // no mbox instructions in 1,2,3,4 1924 mfpr r31, pt0 // no mbox instructions in 1,2,3,4 1925 mfpr r31, pt0 // no mbox instructions in 1,2,3,4 1926 mfpr r31, pt0 // no mbox instructions in 1,2,3,4 1927 1928 lda r8, 0(r31) // flood the dcache with junk data 1929no_pm_change_5_: ldqp r31, 0(r8) 1930 lda r8, 0x20(r8) // touch each cache block 1931 srl r8, 13, r9 1932 blbc r9, no_pm_change_5_ 1933 1934 mb // ensure no outstanding fills 1935 mtpr r31, dc_mode // turn the dcache back off 1936 nop // force correct slotting 1937 mfpr r31, pt0 // no hw_rei_stall in 0,1 1938#endif 1939 1940 | |
| 1941no_pm_change_10_: hw_rei_stall // back we go 1942 1943 ALIGN_BLOCK | 1247no_pm_change_10_: hw_rei_stall // back we go 1248 1249 ALIGN_BLOCK |
| 1944//+ | 1250// |
| 1945// swppal_cont - finish up the swppal call_pal | 1251// swppal_cont - finish up the swppal call_pal |
| 1946//- | 1252// |
| 1947 1948swppal_cont: 1949 mfpr r2, pt_misc // get misc bits 1950 sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit 1951 or r2, r0, r2 // set the bit 1952 mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel) 1953 mtpr r2, pt_misc // update the chip 1954 --- 16 unchanged lines hidden (view full) --- 1971swppal_fail: 1972 addq r0, 1, r0 // set unknown pal or not loaded 1973 hw_rei // and return 1974 1975 1976// .sbttl "Memory management" 1977 1978 ALIGN_BLOCK | 1253 1254swppal_cont: 1255 mfpr r2, pt_misc // get misc bits 1256 sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit 1257 or r2, r0, r2 // set the bit 1258 mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel) 1259 mtpr r2, pt_misc // update the chip 1260 --- 16 unchanged lines hidden (view full) --- 1277swppal_fail: 1278 addq r0, 1, r0 // set unknown pal or not loaded 1279 hw_rei // and return 1280 1281 1282// .sbttl "Memory management" 1283 1284 ALIGN_BLOCK |
| 1979//+ | 1285// |
| 1980//foe_ipte_handler 1981// IFOE detected on level 3 pte, sort out FOE vs ACV 1982// 1983// on entry: 1984// with 1985// R8 = pte 1986// R10 = pc 1987// 1988// Function 1989// Determine TNV vs ACV vs FOE. Build stack and dispatch 1990// Will not be here if TNV. | 1286//foe_ipte_handler 1287// IFOE detected on level 3 pte, sort out FOE vs ACV 1288// 1289// on entry: 1290// with 1291// R8 = pte 1292// R10 = pc 1293// 1294// Function 1295// Determine TNV vs ACV vs FOE. Build stack and dispatch 1296// Will not be here if TNV. |
| 1991//- | 1297// |
| 1992 1993foe_ipte_handler: 1994 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1995 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1996 1997 bis r11, r31, r12 // Save PS for stack write 1998 bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern 1999 --- 31 unchanged lines hidden (view full) --- 2031 2032 stq r29, osfsf_gp(sp) 2033 mtpr r13, exc_addr // set vector address 2034 2035 mfpr r29, pt_kgp // load kgp 2036 hw_rei_spe // out to exec 2037 2038 ALIGN_BLOCK | 1298 1299foe_ipte_handler: 1300 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1301 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1302 1303 bis r11, r31, r12 // Save PS for stack write 1304 bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern 1305 --- 31 unchanged lines hidden (view full) --- 1337 1338 stq r29, osfsf_gp(sp) 1339 mtpr r13, exc_addr // set vector address 1340 1341 mfpr r29, pt_kgp // load kgp 1342 hw_rei_spe // out to exec 1343 1344 ALIGN_BLOCK |
| 2039//+ | 1345// |
| 2040//invalid_ipte_handler 2041// TNV detected on level 3 pte, sort out TNV vs ACV 2042// 2043// on entry: 2044// with 2045// R8 = pte 2046// R10 = pc 2047// 2048// Function 2049// Determine TNV vs ACV. Build stack and dispatch. | 1346//invalid_ipte_handler 1347// TNV detected on level 3 pte, sort out TNV vs ACV 1348// 1349// on entry: 1350// with 1351// R8 = pte 1352// R10 = pc 1353// 1354// Function 1355// Determine TNV vs ACV. Build stack and dispatch. |
| 2050//- | 1356// |
| 2051 2052invalid_ipte_handler: 2053 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 2054 mtpr r31, ev5__ps // Set Ibox current mode to kernel 2055 2056 bis r11, r31, r12 // Save PS for stack write 2057 bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern 2058 --- 34 unchanged lines hidden (view full) --- 2093 2094 mfpr r29, pt_kgp // load kgp 2095 hw_rei_spe // out to exec 2096 2097 2098 2099 2100 ALIGN_BLOCK | 1357 1358invalid_ipte_handler: 1359 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1360 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1361 1362 bis r11, r31, r12 // Save PS for stack write 1363 bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern 1364 --- 34 unchanged lines hidden (view full) --- 1399 1400 mfpr r29, pt_kgp // load kgp 1401 hw_rei_spe // out to exec 1402 1403 1404 1405 1406 ALIGN_BLOCK |
| 2101//+ | 1407// |
| 2102//invalid_dpte_handler 2103// INVALID detected on level 3 pte, sort out TNV vs ACV 2104// 2105// on entry: 2106// with 2107// R10 = va 2108// R8 = pte 2109// R9 = mm_stat 2110// PT6 = pc 2111// 2112// Function 2113// Determine TNV vs ACV. Build stack and dispatch | 1408//invalid_dpte_handler 1409// INVALID detected on level 3 pte, sort out TNV vs ACV 1410// 1411// on entry: 1412// with 1413// R10 = va 1414// R8 = pte 1415// R9 = mm_stat 1416// PT6 = pc 1417// 1418// Function 1419// Determine TNV vs ACV. Build stack and dispatch |
| 2114//- | 1420// |
| 2115 2116 2117invalid_dpte_handler: 2118 mfpr r12, pt6 2119 blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode 2120 2121 bis r12, r31, r14 // save PC in case of tbmiss or fault 2122 srl r9, mm_stat_v_opcode, r25 // shift opc to <0> --- 57 unchanged lines hidden (view full) --- 2180 stq r25, osfsf_ps(sp) // save ps 2181 mtpr r13, exc_addr // set vector address 2182 2183 mfpr r29, pt_kgp // load kgp 2184 cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv 2185 2186 hw_rei_spe // out to exec 2187 | 1421 1422 1423invalid_dpte_handler: 1424 mfpr r12, pt6 1425 blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode 1426 1427 bis r12, r31, r14 // save PC in case of tbmiss or fault 1428 srl r9, mm_stat_v_opcode, r25 // shift opc to <0> --- 57 unchanged lines hidden (view full) --- 1486 stq r25, osfsf_ps(sp) // save ps 1487 mtpr r13, exc_addr // set vector address 1488 1489 mfpr r29, pt_kgp // load kgp 1490 cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv 1491 1492 hw_rei_spe // out to exec 1493 |
| 2188//+ | |
| 2189// | 1494// |
| 1495// |
|
| 2190// We come here if we are erring on a dtb_miss, and the instr is a 2191// fetch, fetch_m, of load to r31/f31. 2192// The PC is incremented, and we return to the program. 2193// essentially ignoring the instruction and error. 2194// | 1496// We come here if we are erring on a dtb_miss, and the instr is a 1497// fetch, fetch_m, of load to r31/f31. 1498// The PC is incremented, and we return to the program. 1499// essentially ignoring the instruction and error. 1500// |
| 2195//- | 1501// |
| 2196 ALIGN_BLOCK 2197nmiss_fetch_ldr31_err: 2198 mfpr r12, pt6 2199 addq r12, 4, r12 // bump pc to pc+4 2200 2201 mtpr r12, exc_addr // and set entry point 2202 mfpr r31, pt0 // pad exc_addr write 2203 2204 hw_rei // 2205 2206 ALIGN_BLOCK | 1502 ALIGN_BLOCK 1503nmiss_fetch_ldr31_err: 1504 mfpr r12, pt6 1505 addq r12, 4, r12 // bump pc to pc+4 1506 1507 mtpr r12, exc_addr // and set entry point 1508 mfpr r31, pt0 // pad exc_addr write 1509 1510 hw_rei // 1511 1512 ALIGN_BLOCK |
| 2207//+ | 1513// |
| 2208// double_pte_inv 2209// We had a single tbmiss which turned into a double tbmiss which found 2210// an invalid PTE. Return to single miss with a fake pte, and the invalid 2211// single miss flow will report the error. 2212// 2213// on entry: 2214// r21 PTE 2215// r22 available 2216// VA IPR locked with original fault VA 2217// pt4 saved r21 2218// pt5 saved r22 2219// pt6 original exc_addr 2220// 2221// on return to tbmiss flow: 2222// r8 fake PTE 2223// 2224// | 1514// double_pte_inv 1515// We had a single tbmiss which turned into a double tbmiss which found 1516// an invalid PTE. Return to single miss with a fake pte, and the invalid 1517// single miss flow will report the error. 1518// 1519// on entry: 1520// r21 PTE 1521// r22 available 1522// VA IPR locked with original fault VA 1523// pt4 saved r21 1524// pt5 saved r22 1525// pt6 original exc_addr 1526// 1527// on return to tbmiss flow: 1528// r8 fake PTE 1529// 1530// |
| 2225//- | 1531// |
| 2226double_pte_inv: 2227 srl r21, osfpte_v_kre, r21 // get the kre bit to <0> 2228 mfpr r22, exc_addr // get the pc 2229 2230 lda r22, 4(r22) // inc the pc 2231 lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set 2232 2233 cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0 2234 mtpr r22, exc_addr // set for rei 2235 2236 mfpr r21, pt4 // restore regs 2237 mfpr r22, pt5 // restore regs 2238 2239 hw_rei // back to tb miss 2240 2241 ALIGN_BLOCK | 1532double_pte_inv: 1533 srl r21, osfpte_v_kre, r21 // get the kre bit to <0> 1534 mfpr r22, exc_addr // get the pc 1535 1536 lda r22, 4(r22) // inc the pc 1537 lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set 1538 1539 cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0 1540 mtpr r22, exc_addr // set for rei 1541 1542 mfpr r21, pt4 // restore regs 1543 mfpr r22, pt5 // restore regs 1544 1545 hw_rei // back to tb miss 1546 1547 ALIGN_BLOCK |
| 2242//+ | 1548// |
| 2243//tnv_in_pal 2244// The only places in pal that ld or store are the 2245// stack builders, rti or retsys. Any of these mean we 2246// need to take a ksp not valid halt. 2247// | 1549//tnv_in_pal 1550// The only places in pal that ld or store are the 1551// stack builders, rti or retsys. Any of these mean we 1552// need to take a ksp not valid halt. 1553// |
| 2248//- | 1554// |
| 2249tnv_in_pal: 2250 2251 2252 br r31, ksp_inval_halt 2253 2254 2255// .sbttl "Icache flush routines" 2256 2257 ALIGN_BLOCK | 1555tnv_in_pal: 1556 1557 1558 br r31, ksp_inval_halt 1559 1560 1561// .sbttl "Icache flush routines" 1562 1563 ALIGN_BLOCK |
| 2258//+ | 1564// |
| 2259// Common Icache flush routine. 2260// 2261// | 1565// Common Icache flush routine. 1566// 1567// |
| 2262//- | 1568// |
| 2263pal_ic_flush: 2264 nop 2265 mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 2266 nop 2267 nop 2268 2269// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) 2270 nop --- 51 unchanged lines hidden (view full) --- 2322 nop 2323 2324one_cycle_and_hw_rei: 2325 nop 2326 nop 2327 2328 hw_rei_stall 2329 | 1569pal_ic_flush: 1570 nop 1571 mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 1572 nop 1573 nop 1574 1575// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) 1576 nop --- 51 unchanged lines hidden (view full) --- 1628 nop 1629 1630one_cycle_and_hw_rei: 1631 nop 1632 nop 1633 1634 hw_rei_stall 1635 |
| 2330#if icflush_on_tbix != 0 2331 2332 | |
| 2333 ALIGN_BLOCK | 1636 ALIGN_BLOCK |
| 2334 2335//+ 2336// Common Icache flush and ITB invalidate single routine. 2337// ITBIS and hw_rei_stall must be in same octaword. 2338// r17 - has address to invalidate | |
| 2339// | 1637// |
| 2340//- 2341PAL_IC_FLUSH_AND_TBISI: 2342 nop 2343 mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 2344 nop 2345 nop 2346 2347// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) 2348 nop 2349 nop 2350 nop 2351 nop 2352 2353 nop 2354 nop 2355 nop 2356 nop 2357 2358 nop 2359 nop // 10 2360 2361 nop 2362 nop 2363 nop 2364 nop 2365 2366 nop 2367 nop 2368 nop 2369 nop 2370 2371 nop 2372 nop // 20 2373 2374 nop 2375 nop 2376 nop 2377 nop 2378 2379 nop 2380 nop 2381 nop 2382 nop 2383 2384 nop 2385 nop // 30 2386 nop 2387 nop 2388 nop 2389 nop 2390 2391 nop 2392 nop 2393 nop 2394 nop 2395 2396 nop 2397 nop // 40 2398 2399 2400 nop 2401 nop 2402 2403 nop 2404 nop 2405 2406 // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions 2407 // 44 nops plus 4 instructions before it is 48 instructions. 2408 // Since this routine started on a 32-byte (8 instruction) boundary, 2409 // the following 2 instructions will be in the same octword as required. 2410// ALIGN_BRANCH 2411 mtpr r17, ev5__itb_is // Flush ITB 2412 hw_rei_stall 2413 2414#endif 2415 2416 ALIGN_BLOCK 2417//+ | |
| 2418//osfpal_calpal_opcdec 2419// Here for all opcdec CALL_PALs 2420// 2421// Build stack frame 2422// a0 <- code 2423// a1 <- unpred 2424// a2 <- unpred 2425// vector via entIF 2426// | 1638//osfpal_calpal_opcdec 1639// Here for all opcdec CALL_PALs 1640// 1641// Build stack frame 1642// a0 <- code 1643// a1 <- unpred 1644// a2 <- unpred 1645// vector via entIF 1646// |
| 2427//- | 1647// |
| 2428 2429osfpal_calpal_opcdec: 2430 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 2431 mtpr r31, ev5__ps // Set Ibox current mode to kernel 2432 2433 mfpr r14, exc_addr // get pc 2434 nop 2435 --- 32 unchanged lines hidden (view full) --- 2468 2469 2470 hw_rei_spe // done 2471 2472 2473 2474 2475 | 1648 1649osfpal_calpal_opcdec: 1650 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 1651 mtpr r31, ev5__ps // Set Ibox current mode to kernel 1652 1653 mfpr r14, exc_addr // get pc 1654 nop 1655 --- 32 unchanged lines hidden (view full) --- 1688 1689 1690 hw_rei_spe // done 1691 1692 1693 1694 1695 |
| 2476//+ | 1696// |
| 2477//pal_update_pcb 2478// Update the PCB with the current SP, AST, and CC info 2479// 2480// r0 - return linkage | 1697//pal_update_pcb 1698// Update the PCB with the current SP, AST, and CC info 1699// 1700// r0 - return linkage |
| 2481//- | 1701// |
| 2482 ALIGN_BLOCK 2483 2484pal_update_pcb: 2485 mfpr r12, pt_pcbb // get pcbb 2486 and r11, osfps_m_mode, r25 // get mode 2487 beq r25, pal_update_pcb_10_ // in kern? no need to update user sp 2488 mtpr r30, pt_usp // save user stack | 1702 ALIGN_BLOCK 1703 1704pal_update_pcb: 1705 mfpr r12, pt_pcbb // get pcbb 1706 and r11, osfps_m_mode, r25 // get mode 1707 beq r25, pal_update_pcb_10_ // in kern? no need to update user sp 1708 mtpr r30, pt_usp // save user stack |
| 2489 stqp r30, osfpcb_q_usp(r12) // store usp | 1709 stq_p r30, osfpcb_q_usp(r12) // store usp |
| 2490 br r31, pal_update_pcb_20_ // join common | 1710 br r31, pal_update_pcb_20_ // join common |
| 2491pal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp | 1711pal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp |
| 2492pal_update_pcb_20_: rpcc r13 // get cyccounter 2493 srl r13, 32, r14 // move offset 2494 addl r13, r14, r14 // merge for new time | 1712pal_update_pcb_20_: rpcc r13 // get cyccounter 1713 srl r13, 32, r14 // move offset 1714 addl r13, r14, r14 // merge for new time |
| 2495 stlp r14, osfpcb_l_cc(r12) // save time | 1715 stl_p r14, osfpcb_l_cc(r12) // save time |
| 2496 2497//orig pvc_jsr updpcb, bsr=1, dest=1 2498 ret r31, (r0) 2499 2500 | 1716 1717//orig pvc_jsr updpcb, bsr=1, dest=1 1718 ret r31, (r0) 1719 1720 |
| 2501 2502#if remove_save_state == 0 2503 2504// .sbttl "PAL_SAVE_STATE" 2505//+ | |
| 2506// | 1721// |
| 2507// Pal_save_state | 1722// pal_save_state |
| 2508// 2509// Function 2510// All chip state saved, all PT's, SR's FR's, IPR's 2511// 2512// 2513// Regs' on entry... 2514// 2515// R0 = halt code --- 4 unchanged lines hidden (view full) --- 2520// pt5 = r3 2521// 2522// register usage: 2523// r0 = halt_code 2524// r1 = addr of impure area 2525// r3 = return_address 2526// r4 = scratch 2527// | 1723// 1724// Function 1725// All chip state saved, all PT's, SR's FR's, IPR's 1726// 1727// 1728// Regs' on entry... 1729// 1730// R0 = halt code --- 4 unchanged lines hidden (view full) --- 1735// pt5 = r3 1736// 1737// register usage: 1738// r0 = halt_code 1739// r1 = addr of impure area 1740// r3 = return_address 1741// r4 = scratch 1742// |
| 2528//- | 1743// |
| 2529 | 1744 |
| 2530 | |
| 2531 ALIGN_BLOCK 2532 .globl pal_save_state 2533pal_save_state: 2534// 2535// 2536// start of implementation independent save routine 2537// 2538// the impure area is larger than the addressibility of hw_ld and hw_st --- 37 unchanged lines hidden (view full) --- 2576 // r2 has been saved 2577 // r3 has been saved 2578 // pt0, pt4, pt5 have been lost 2579 2580 // 2581 // Get out of shadow mode 2582 // 2583 | 1745 ALIGN_BLOCK 1746 .globl pal_save_state 1747pal_save_state: 1748// 1749// 1750// start of implementation independent save routine 1751// 1752// the impure area is larger than the addressibility of hw_ld and hw_st --- 37 unchanged lines hidden (view full) --- 1790 // r2 has been saved 1791 // r3 has been saved 1792 // pt0, pt4, pt5 have been lost 1793 1794 // 1795 // Get out of shadow mode 1796 // 1797 |
| 2584 mfpr r2, icsr // Get icsr //orig 2585//orig ldah r0, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location | 1798 mfpr r2, icsr // Get icsr |
| 2586 ldah r0, (1<<(icsr_v_sde-16))(r31) | 1799 ldah r0, (1<<(icsr_v_sde-16))(r31) |
| 2587 bic r2, r0, r0 // ICSR with SDE clear //orig 2588 mtpr r0, icsr // Turn off SDE //orig | 1800 bic r2, r0, r0 // ICSR with SDE clear 1801 mtpr r0, icsr // Turn off SDE |
| 2589 | 1802 |
| 2590 mfpr r31, pt0 // SDE bubble cycle 1 //orig 2591 mfpr r31, pt0 // SDE bubble cycle 2 //orig 2592 mfpr r31, pt0 // SDE bubble cycle 3 //orig 2593 nop //orig | 1803 mfpr r31, pt0 // SDE bubble cycle 1 1804 mfpr r31, pt0 // SDE bubble cycle 2 1805 mfpr r31, pt0 // SDE bubble cycle 3 1806 nop |
| 2594 2595 2596 // save integer regs R4-r31 | 1807 1808 1809 // save integer regs R4-r31 |
| 2597//orig #define t 4 2598//orig .repeat 28 2599//orig store_reg \t 2600//orig #define t t + 1 2601//orig .endr | |
| 2602 SAVE_GPR(r4,CNS_Q_GPR+0x20,r1) 2603 SAVE_GPR(r5,CNS_Q_GPR+0x28,r1) 2604 SAVE_GPR(r6,CNS_Q_GPR+0x30,r1) 2605 SAVE_GPR(r7,CNS_Q_GPR+0x38,r1) 2606 SAVE_GPR(r8,CNS_Q_GPR+0x40,r1) 2607 SAVE_GPR(r9,CNS_Q_GPR+0x48,r1) 2608 SAVE_GPR(r10,CNS_Q_GPR+0x50,r1) 2609 SAVE_GPR(r11,CNS_Q_GPR+0x58,r1) --- 17 unchanged lines hidden (view full) --- 2627 SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1) 2628 SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1) 2629 SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1) 2630 2631 // save all paltemp regs except pt0 2632 2633//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores 2634//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores | 1810 SAVE_GPR(r4,CNS_Q_GPR+0x20,r1) 1811 SAVE_GPR(r5,CNS_Q_GPR+0x28,r1) 1812 SAVE_GPR(r6,CNS_Q_GPR+0x30,r1) 1813 SAVE_GPR(r7,CNS_Q_GPR+0x38,r1) 1814 SAVE_GPR(r8,CNS_Q_GPR+0x40,r1) 1815 SAVE_GPR(r9,CNS_Q_GPR+0x48,r1) 1816 SAVE_GPR(r10,CNS_Q_GPR+0x50,r1) 1817 SAVE_GPR(r11,CNS_Q_GPR+0x58,r1) --- 17 unchanged lines hidden (view full) --- 1835 SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1) 1836 SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1) 1837 SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1) 1838 1839 // save all paltemp regs except pt0 1840 1841//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores 1842//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores |
| 2635//orig #define t 1 2636//orig .repeat 23 2637//orig store_reg \t , pal=1 2638//orig #define t t + 1 2639//orig .endr | |
| 2640 2641 lda r1, -0x200(r1) // Restore the impure base address. 2642 lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area. 2643 SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 2644 SAVE_IPR(pt1,CNS_Q_PT+0x08,r1) 2645 SAVE_IPR(pt2,CNS_Q_PT+0x10,r1) 2646 SAVE_IPR(pt3,CNS_Q_PT+0x18,r1) 2647 SAVE_IPR(pt4,CNS_Q_PT+0x20,r1) --- 13 unchanged lines hidden (view full) --- 2661 SAVE_IPR(pt18,CNS_Q_PT+0x90,r1) 2662 SAVE_IPR(pt19,CNS_Q_PT+0x98,r1) 2663 SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1) 2664 SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1) 2665 SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1) 2666 SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1) 2667 2668 // Restore shadow mode | 1843 1844 lda r1, -0x200(r1) // Restore the impure base address. 1845 lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area. 1846 SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 1847 SAVE_IPR(pt1,CNS_Q_PT+0x08,r1) 1848 SAVE_IPR(pt2,CNS_Q_PT+0x10,r1) 1849 SAVE_IPR(pt3,CNS_Q_PT+0x18,r1) 1850 SAVE_IPR(pt4,CNS_Q_PT+0x20,r1) --- 13 unchanged lines hidden (view full) --- 1864 SAVE_IPR(pt18,CNS_Q_PT+0x90,r1) 1865 SAVE_IPR(pt19,CNS_Q_PT+0x98,r1) 1866 SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1) 1867 SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1) 1868 SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1) 1869 SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1) 1870 1871 // Restore shadow mode |
| 2669 mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig 2670 mfpr r31, pt0 //orig 2671 mtpr r2, icsr // Restore original ICSR //orig | 1872 mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) 1873 mfpr r31, pt0 1874 mtpr r2, icsr // Restore original ICSR |
| 2672 | 1875 |
| 2673 mfpr r31, pt0 // SDE bubble cycle 1 //orig 2674 mfpr r31, pt0 // SDE bubble cycle 2 //orig 2675 mfpr r31, pt0 // SDE bubble cycle 3 //orig 2676 nop //orig | 1876 mfpr r31, pt0 // SDE bubble cycle 1 1877 mfpr r31, pt0 // SDE bubble cycle 2 1878 mfpr r31, pt0 // SDE bubble cycle 3 1879 nop |
| 2677 2678 // save all integer shadow regs | 1880 1881 // save all integer shadow regs |
| 2679 2680//orig #define t 8 2681//orig .repeat 7 2682//orig store_reg \t, shadow=1 2683//orig #define t t + 1 2684//orig .endr 2685//orig store_reg 25, shadow=1 2686 | |
| 2687 SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 2688 SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 2689 SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 2690 SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 2691 SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 2692 SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 2693 SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 2694 SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 2695 | 1882 SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 1883 SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 1884 SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 1885 SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 1886 SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 1887 SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 1888 SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 1889 SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 1890 |
| 2696//orig store_reg exc_addr, ipr=1 // save ipr 2697//orig store_reg pal_base, ipr=1 // save ipr 2698//orig store_reg mm_stat, ipr=1 // save ipr 2699//orig store_reg va, ipr=1 // save ipr 2700//orig store_reg icsr, ipr=1 // save ipr 2701//orig store_reg ipl, ipr=1 // save ipr 2702//orig store_reg ps, ipr=1 // save ipr 2703//orig store_reg itb_asn, ipr=1 // save ipr 2704//orig store_reg aster, ipr=1 // save ipr 2705//orig store_reg astrr, ipr=1 // save ipr 2706//orig store_reg sirr, ipr=1 // save ipr 2707//orig store_reg isr, ipr=1 // save ipr 2708//orig store_reg ivptbr, ipr=1 // save ipr 2709//orig store_reg mcsr, ipr=1 // save ipr 2710//orig store_reg dc_mode, ipr=1 // save ipr 2711 | |
| 2712 SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) 2713 SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1) 2714 SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1) 2715 SAVE_IPR(va,CNS_Q_VA,r1) 2716 SAVE_IPR(icsr,CNS_Q_ICSR,r1) 2717 SAVE_IPR(ipl,CNS_Q_IPL,r1) 2718 SAVE_IPR(ips,CNS_Q_IPS,r1) 2719 SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) --- 9 unchanged lines hidden (view full) --- 2729//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for 2730//orig // PVC violation applies only to 2731pvc$osf35$379: // loads. HW_ST ok here, so ignore 2732 SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2 2733 2734 2735 //the following iprs are informational only -- will not be restored 2736 | 1891 SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) 1892 SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1) 1893 SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1) 1894 SAVE_IPR(va,CNS_Q_VA,r1) 1895 SAVE_IPR(icsr,CNS_Q_ICSR,r1) 1896 SAVE_IPR(ipl,CNS_Q_IPL,r1) 1897 SAVE_IPR(ips,CNS_Q_IPS,r1) 1898 SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) --- 9 unchanged lines hidden (view full) --- 1908//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for 1909//orig // PVC violation applies only to 1910pvc$osf35$379: // loads. HW_ST ok here, so ignore 1911 SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2 1912 1913 1914 //the following iprs are informational only -- will not be restored 1915 |
| 2737//orig store_reg icperr_stat, ipr=1 2738//orig store_reg pmctr, ipr=1 2739//orig store_reg intid, ipr=1 2740//orig store_reg exc_sum, ipr=1 2741//orig store_reg exc_mask, ipr=1 2742//orig ldah r14, 0xfff0(r31) 2743//orig zap r14, 0xE0, r14 // Get Cbox IPR base 2744//orig nop // pad mf dcperr_stat out of shadow of last store 2745//orig nop 2746//orig nop 2747//orig store_reg dcperr_stat, ipr=1 2748 | |
| 2749 SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1) 2750 SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1) 2751 SAVE_IPR(intId,CNS_Q_INT_ID,r1) 2752 SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1) 2753 SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1) 2754 ldah r14, 0xFFF0(zero) 2755 zap r14, 0xE0, r14 // Get base address of CBOX IPRs 2756 NOP // Pad mfpr dcPerr out of shadow of 2757 NOP // last store 2758 NOP 2759 SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1) 2760 2761 // read cbox ipr state 2762 | 1916 SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1) 1917 SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1) 1918 SAVE_IPR(intId,CNS_Q_INT_ID,r1) 1919 SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1) 1920 SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1) 1921 ldah r14, 0xFFF0(zero) 1922 zap r14, 0xE0, r14 // Get base address of CBOX IPRs 1923 NOP // Pad mfpr dcPerr out of shadow of 1924 NOP // last store 1925 NOP 1926 SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1) 1927 1928 // read cbox ipr state 1929 |
| 2763//orig mb 2764//orig ldqp r2, ev5__sc_ctl(r14) 2765//orig ldqp r13, ld_lock(r14) 2766//orig ldqp r4, ev5__sc_addr(r14) 2767//orig ldqp r5, ev5__ei_addr(r14) 2768//orig ldqp r6, ev5__bc_tag_addr(r14) 2769//orig ldqp r7, ev5__fill_syn(r14) 2770//orig bis r5, r4, r31 2771//orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them 2772//orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr 2773//orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn 2774//orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked 2775//orig mb 2776 2777#ifndef SIMOS | |
| 2778 mb 2779 ldq_p r2, scCtl(r14) 2780 ldq_p r13, ldLock(r14) 2781 ldq_p r4, scAddr(r14) 2782 ldq_p r5, eiAddr(r14) 2783 ldq_p r6, bcTagAddr(r14) 2784 ldq_p r7, fillSyn(r14) 2785 bis r5, r4, zero // Make sure all loads complete before 2786 bis r7, r6, zero // reading registers that unlock them. 2787 ldq_p r8, scStat(r14) // Unlocks scAddr. 2788 ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn. 2789 ldq_p zero, eiStat(r14) // Make sure it is really unlocked. 2790 mb | 1930 mb 1931 ldq_p r2, scCtl(r14) 1932 ldq_p r13, ldLock(r14) 1933 ldq_p r4, scAddr(r14) 1934 ldq_p r5, eiAddr(r14) 1935 ldq_p r6, bcTagAddr(r14) 1936 ldq_p r7, fillSyn(r14) 1937 bis r5, r4, zero // Make sure all loads complete before 1938 bis r7, r6, zero // reading registers that unlock them. 1939 ldq_p r8, scStat(r14) // Unlocks scAddr. 1940 ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn. 1941 ldq_p zero, eiStat(r14) // Make sure it is really unlocked. 1942 mb |
| 2791#endif 2792//orig // save cbox ipr state 2793//orig store_reg1 sc_ctl, r2, r1, ipr=1 2794//orig store_reg1 ld_lock, r13, r1, ipr=1 2795//orig store_reg1 sc_addr, r4, r1, ipr=1 2796//orig store_reg1 ei_addr, r5, r1, ipr=1 2797//orig store_reg1 bc_tag_addr, r6, r1, ipr=1 2798//orig store_reg1 fill_syn, r7, r1, ipr=1 2799//orig store_reg1 sc_stat, r8, r1, ipr=1 2800//orig store_reg1 ei_stat, r9, r1, ipr=1 2801//orig //bc_config? sl_rcv? | |
| 2802 | 1943 |
| 1944 // save cbox ipr state |
|
| 2803 SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1); 2804 SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1); 2805 SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1); 2806 SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1); 2807 SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1); 2808 SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1); 2809 SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1); 2810 SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1); | 1945 SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1); 1946 SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1); 1947 SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1); 1948 SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1); 1949 SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1); 1950 SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1); 1951 SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1); 1952 SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1); |
| 1953 //bc_config? sl_rcv? |
|
| 2811 | 1954 |
| 2812// restore impure base //orig | 1955// restore impure base |
| 2813//orig unfix_impure_ipr r1 2814 lda r1, -CNS_Q_IPR(r1) 2815 | 1956//orig unfix_impure_ipr r1 1957 lda r1, -CNS_Q_IPR(r1) 1958 |
| 2816// save all floating regs //orig 2817 mfpr r0, icsr // get icsr //orig 2818 or r31, 1, r2 // get a one //orig 2819//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig | 1959// save all floating regs 1960 mfpr r0, icsr // get icsr 1961 or r31, 1, r2 // get a one |
| 2820 sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position | 1962 sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position |
| 2821 or r2, r0, r0 // set FEN on //orig 2822 mtpr r0, icsr // write to icsr, enabling FEN //orig | 1963 or r2, r0, r0 // set FEN on 1964 mtpr r0, icsr // write to icsr, enabling FEN |
| 2823 2824// map the save area virtually | 1965 1966// map the save area virtually |
| 2825// orig mtpr r31, dtb_ia // clear the dtb 2826// orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA 2827// orig sll r0, 32, r0 // shift to PFN field 2828// orig lda r2, 0xff(r31) // all read enable and write enable bits set 2829// orig sll r2, 8, r2 // move to PTE location 2830// orig addq r0, r2, r0 // combine with PFN 2831// orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 2832// orig mtpr r1, dtb_tag // write TB tag 2833 | |
| 2834 mtpr r31, dtbIa // Clear all DTB entries 2835 srl r1, va_s_off, r0 // Clean off byte-within-page offset 2836 sll r0, pte_v_pfn, r0 // Shift to form PFN 2837 lda r0, pte_m_prot(r0) // Set all read/write enable bits 2838 mtpr r0, dtbPte // Load the PTE and set valid 2839 mtpr r1, dtbTag // Write the PTE and tag into the DTB 2840 2841 | 1967 mtpr r31, dtbIa // Clear all DTB entries 1968 srl r1, va_s_off, r0 // Clean off byte-within-page offset 1969 sll r0, pte_v_pfn, r0 // Shift to form PFN 1970 lda r0, pte_m_prot(r0) // Set all read/write enable bits 1971 mtpr r0, dtbPte // Load the PTE and set valid 1972 mtpr r1, dtbTag // Write the PTE and tag into the DTB 1973 1974 |
| 2842//orig // map the next page too - in case the impure area crosses a page boundary 2843//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page 2844//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA 2845//orig sll r0, 32, r0 // shift to PFN field 2846//orig lda r2, 0xff(r31) // all read enable and write enable bits set 2847//orig sll r2, 8, r2 // move to PTE location 2848//orig addq r0, r2, r0 // combine with PFN 2849//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 2850//orig mtpr r4, dtb_tag // write TB tag 2851 | 1975// map the next page too - in case the impure area crosses a page boundary |
| 2852 lda r4, (1<<va_s_off)(r1) // Generate address for next page 2853 srl r4, va_s_off, r0 // Clean off byte-within-page offset 2854 sll r0, pte_v_pfn, r0 // Shift to form PFN 2855 lda r0, pte_m_prot(r0) // Set all read/write enable bits 2856 mtpr r0, dtbPte // Load the PTE and set valid 2857 mtpr r4, dtbTag // Write the PTE and tag into the DTB 2858 | 1976 lda r4, (1<<va_s_off)(r1) // Generate address for next page 1977 srl r4, va_s_off, r0 // Clean off byte-within-page offset 1978 sll r0, pte_v_pfn, r0 // Shift to form PFN 1979 lda r0, pte_m_prot(r0) // Set all read/write enable bits 1980 mtpr r0, dtbPte // Load the PTE and set valid 1981 mtpr r4, dtbTag // Write the PTE and tag into the DTB 1982 |
| 2859 sll r31, 0, r31 // stall cycle 1 // orig 2860 sll r31, 0, r31 // stall cycle 2 // orig 2861 sll r31, 0, r31 // stall cycle 3 // orig 2862 nop // orig | 1983 sll r31, 0, r31 // stall cycle 1 1984 sll r31, 0, r31 // stall cycle 2 1985 sll r31, 0, r31 // stall cycle 3 1986 nop |
| 2863 | 1987 |
| 2864//orig // add offset for saving fpr regs | 1988// add offset for saving fpr regs |
| 2865//orig fix_impure_gpr r1 | 1989//orig fix_impure_gpr r1 |
| 2866 | |
| 2867 lda r1, 0x200(r1) // Point to center of CPU segment 2868 2869// now save the regs - F0-F31 | 1990 lda r1, 0x200(r1) // Point to center of CPU segment 1991 1992// now save the regs - F0-F31 |
| 2870 2871//orig #define t 0 2872//orig .repeat 32 2873//orig store_reg \t , fpu=1 2874//orig #define t t + 1 2875//orig .endr 2876 | |
| 2877 mf_fpcr f0 // original 2878 2879 SAVE_FPR(f0,CNS_Q_FPR+0x00,r1) 2880 SAVE_FPR(f1,CNS_Q_FPR+0x08,r1) 2881 SAVE_FPR(f2,CNS_Q_FPR+0x10,r1) 2882 SAVE_FPR(f3,CNS_Q_FPR+0x18,r1) 2883 SAVE_FPR(f4,CNS_Q_FPR+0x20,r1) 2884 SAVE_FPR(f5,CNS_Q_FPR+0x28,r1) --- 19 unchanged lines hidden (view full) --- 2904 SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1) 2905 SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1) 2906 SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1) 2907 SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1) 2908 SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1) 2909 SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1) 2910 SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1) 2911 | 1993 mf_fpcr f0 // original 1994 1995 SAVE_FPR(f0,CNS_Q_FPR+0x00,r1) 1996 SAVE_FPR(f1,CNS_Q_FPR+0x08,r1) 1997 SAVE_FPR(f2,CNS_Q_FPR+0x10,r1) 1998 SAVE_FPR(f3,CNS_Q_FPR+0x18,r1) 1999 SAVE_FPR(f4,CNS_Q_FPR+0x20,r1) 2000 SAVE_FPR(f5,CNS_Q_FPR+0x28,r1) --- 19 unchanged lines hidden (view full) --- 2020 SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1) 2021 SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1) 2022 SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1) 2023 SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1) 2024 SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1) 2025 SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1) 2026 SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1) 2027 |
| 2912//orig //switch impure offset from gpr to ipr--- | 2028//switch impure offset from gpr to ipr--- |
| 2913//orig unfix_impure_gpr r1 2914//orig fix_impure_ipr r1 2915//orig store_reg1 fpcsr, f0, r1, fpcsr=1 2916 | 2029//orig unfix_impure_gpr r1 2030//orig fix_impure_ipr r1 2031//orig store_reg1 fpcsr, f0, r1, fpcsr=1 2032 |
| 2917 SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach// pb | 2033 SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach |
| 2918 lda r1, -0x200(r1) // Restore the impure base address 2919 | 2034 lda r1, -0x200(r1) // Restore the impure base address 2035 |
| 2920//orig // and back to gpr --- | 2036// and back to gpr --- |
| 2921//orig unfix_impure_ipr r1 2922//orig fix_impure_gpr r1 2923 2924//orig lda r0, cns_mchksize(r31) // get size of mchk area 2925//orig store_reg1 mchkflag, r0, r1, ipr=1 2926//orig mb 2927 2928 lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again --- 7 unchanged lines hidden (view full) --- 2936//orig mb 2937 2938 lda r1, -CNS_Q_IPR(r1) // back to the base 2939 lda r1, 0x200(r1) // Point to center of CPU segment 2940 or r31, 1, r0 // get a one 2941 SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag 2942 mb 2943 | 2037//orig unfix_impure_ipr r1 2038//orig fix_impure_gpr r1 2039 2040//orig lda r0, cns_mchksize(r31) // get size of mchk area 2041//orig store_reg1 mchkflag, r0, r1, ipr=1 2042//orig mb 2043 2044 lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again --- 7 unchanged lines hidden (view full) --- 2052//orig mb 2053 2054 lda r1, -CNS_Q_IPR(r1) // back to the base 2055 lda r1, 0x200(r1) // Point to center of CPU segment 2056 or r31, 1, r0 // get a one 2057 SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag 2058 mb 2059 |
| 2944//orig // restore impure area base | 2060 // restore impure area base |
| 2945//orig unfix_impure_gpr r1 2946 lda r1, -0x200(r1) // Point to center of CPU segment 2947 | 2061//orig unfix_impure_gpr r1 2062 lda r1, -0x200(r1) // Point to center of CPU segment 2063 |
| 2948 mtpr r31, dtb_ia // clear the dtb //orig 2949 mtpr r31, itb_ia // clear the itb //orig | 2064 mtpr r31, dtb_ia // clear the dtb 2065 mtpr r31, itb_ia // clear the itb |
| 2950 2951//orig pvc_jsr savsta, bsr=1, dest=1 2952 ret r31, (r3) // and back we go | 2066 2067//orig pvc_jsr savsta, bsr=1, dest=1 2068 ret r31, (r3) // and back we go |
| 2953#endif | |
| 2954 2955 | 2069 2070 |
| 2956#if remove_restore_state == 0 | |
| 2957 | 2071 |
| 2958 | |
| 2959// .sbttl "PAL_RESTORE_STATE" | 2072// .sbttl "PAL_RESTORE_STATE" |
| 2960//+ | |
| 2961// | 2073// |
| 2074// |
|
| 2962// Pal_restore_state 2963// 2964// 2965// register usage: 2966// r1 = addr of impure area 2967// r3 = return_address 2968// all other regs are scratchable, as they are about to 2969// be reloaded from ram. 2970// 2971// Function: 2972// All chip state restored, all SRs, FRs, PTs, IPRs 2973// *** except R1, R3, PT0, PT4, PT5 *** 2974// | 2075// Pal_restore_state 2076// 2077// 2078// register usage: 2079// r1 = addr of impure area 2080// r3 = return_address 2081// all other regs are scratchable, as they are about to 2082// be reloaded from ram. 2083// 2084// Function: 2085// All chip state restored, all SRs, FRs, PTs, IPRs 2086// *** except R1, R3, PT0, PT4, PT5 *** 2087// |
| 2975//- | 2088// |
| 2976 ALIGN_BLOCK 2977pal_restore_state: 2978 2979//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so. 2980 | 2089 ALIGN_BLOCK 2090pal_restore_state: 2091 2092//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so. 2093 |
| 2981//orig // map the console io area virtually 2982//orig mtpr r31, dtb_ia // clear the dtb 2983//orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA 2984//orig sll r0, 32, r0 // shift to PFN field 2985//orig lda r2, 0xff(r31) // all read enable and write enable bits set 2986//orig sll r2, 8, r2 // move to PTE location 2987//orig addq r0, r2, r0 // combine with PFN 2988//orig 2989//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 2990//orig mtpr r1, dtb_tag // write TB tag 2991//orig 2992 | 2094// map the console io area virtually |
| 2993 mtpr r31, dtbIa // Clear all DTB entries 2994 srl r1, va_s_off, r0 // Clean off byte-within-page offset 2995 sll r0, pte_v_pfn, r0 // Shift to form PFN 2996 lda r0, pte_m_prot(r0) // Set all read/write enable bits 2997 mtpr r0, dtbPte // Load the PTE and set valid 2998 mtpr r1, dtbTag // Write the PTE and tag into the DTB 2999 3000 | 2095 mtpr r31, dtbIa // Clear all DTB entries 2096 srl r1, va_s_off, r0 // Clean off byte-within-page offset 2097 sll r0, pte_v_pfn, r0 // Shift to form PFN 2098 lda r0, pte_m_prot(r0) // Set all read/write enable bits 2099 mtpr r0, dtbPte // Load the PTE and set valid 2100 mtpr r1, dtbTag // Write the PTE and tag into the DTB 2101 2102 |
| 3001//orig // map the next page too, in case impure area crosses page boundary 3002//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page 3003//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA 3004//orig sll r0, 32, r0 // shift to PFN field 3005//orig lda r2, 0xff(r31) // all read enable and write enable bits set 3006//orig sll r2, 8, r2 // move to PTE location 3007//orig addq r0, r2, r0 // combine with PFN 3008//orig 3009//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 3010//orig mtpr r4, dtb_tag // write TB tag - no virtual mbox instruction for 3 cycles 3011 | 2103// map the next page too, in case impure area crosses page boundary |
| 3012 lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page 3013 srl r4, va_s_off, r0 // Clean off byte-within-page offset 3014 sll r0, pte_v_pfn, r0 // Shift to form PFN 3015 lda r0, pte_m_prot(r0) // Set all read/write enable bits 3016 mtpr r0, dtbPte // Load the PTE and set valid 3017 mtpr r4, dtbTag // Write the PTE and tag into the DTB 3018 | 2104 lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page 2105 srl r4, va_s_off, r0 // Clean off byte-within-page offset 2106 sll r0, pte_v_pfn, r0 // Shift to form PFN 2107 lda r0, pte_m_prot(r0) // Set all read/write enable bits 2108 mtpr r0, dtbPte // Load the PTE and set valid 2109 mtpr r4, dtbTag // Write the PTE and tag into the DTB 2110 |
| 3019//orig // save all floating regs 3020//orig mfpr r0, icsr // get icsr 3021//orig// assume ICSR_V_SDE gt <ICSR_V_FPE> // assertion checker 3022//orig or r31, <<1@<ICSR_V_SDE-ICSR_V_FPE>> ! 1>, r2 // set SDE and FPE 3023//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot 3024//orig or r2, r0, r0 // set FEN on 3025//orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr. 3026 | 2111// save all floating regs |
| 3027 mfpr r0, icsr // Get current ICSR 3028 bis zero, 1, r2 // Get a '1' 3029 or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2 3030 sll r2, icsr_v_fpe, r2 // Shift bits into position 3031 bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE> 3032 mtpr r0, icsr // Update the chip 3033 3034 mfpr r31, pt0 // FPE bubble cycle 1 //orig 3035 mfpr r31, pt0 // FPE bubble cycle 2 //orig 3036 mfpr r31, pt0 // FPE bubble cycle 3 //orig 3037 3038//orig fix_impure_ipr r1 3039//orig restore_reg1 fpcsr, f0, r1, fpcsr=1 3040//orig mt_fpcr f0 3041//orig 3042//orig unfix_impure_ipr r1 3043//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access | 2112 mfpr r0, icsr // Get current ICSR 2113 bis zero, 1, r2 // Get a '1' 2114 or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2 2115 sll r2, icsr_v_fpe, r2 // Shift bits into position 2116 bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE> 2117 mtpr r0, icsr // Update the chip 2118 2119 mfpr r31, pt0 // FPE bubble cycle 1 //orig 2120 mfpr r31, pt0 // FPE bubble cycle 2 //orig 2121 mfpr r31, pt0 // FPE bubble cycle 3 //orig 2122 2123//orig fix_impure_ipr r1 2124//orig restore_reg1 fpcsr, f0, r1, fpcsr=1 2125//orig mt_fpcr f0 2126//orig 2127//orig unfix_impure_ipr r1 2128//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access |
| 3044//orig 3045//orig // restore all floating regs 3046//orig#define t 0 3047//orig .repeat 32 3048//orig restore_reg \t , fpu=1 3049//orig#define t t + 1 3050//orig .endr 3051 | |
| 3052 lda r1, 200(r1) // Point to base of IPR area again 3053 RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb 3054 mt_fpcr f0 // original 3055 3056 lda r1, 0x200(r1) // point to center of CPU segment | 2129 lda r1, 200(r1) // Point to base of IPR area again 2130 RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb 2131 mt_fpcr f0 // original 2132 2133 lda r1, 0x200(r1) // point to center of CPU segment |
| 2134 2135// restore all floating regs |
|
| 3057 RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1) 3058 RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1) 3059 RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1) 3060 RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1) 3061 RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1) 3062 RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1) 3063 RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1) 3064 RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1) --- 17 unchanged lines hidden (view full) --- 3082 RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1) 3083 RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1) 3084 RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1) 3085 RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1) 3086 RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1) 3087 RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1) 3088 RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1) 3089 | 2136 RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1) 2137 RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1) 2138 RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1) 2139 RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1) 2140 RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1) 2141 RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1) 2142 RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1) 2143 RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1) --- 17 unchanged lines hidden (view full) --- 2161 RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1) 2162 RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1) 2163 RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1) 2164 RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1) 2165 RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1) 2166 RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1) 2167 RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1) 2168 |
| 3090//orig // switch impure pointer from gpr to ipr area -- | 2169// switch impure pointer from gpr to ipr area -- |
| 3091//orig unfix_impure_gpr r1 3092//orig fix_impure_ipr r1 | 2170//orig unfix_impure_gpr r1 2171//orig fix_impure_ipr r1 |
| 3093//orig 3094//orig // restore all pal regs 3095//orig#define t 1 3096//orig .repeat 23 3097//orig restore_reg \t , pal=1 3098//orig#define t t + 1 3099//orig .endr 3100 | |
| 3101 lda r1, -0x200(r1) // Restore base address of impure area. 3102 lda r1, CNS_Q_IPR(r1) // Point to base of IPR area. | 2172 lda r1, -0x200(r1) // Restore base address of impure area. 2173 lda r1, CNS_Q_IPR(r1) // Point to base of IPR area. |
| 2174 2175// restore all pal regs |
|
| 3103 RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 3104 RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1) 3105 RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1) 3106 RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1) 3107 RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1) 3108 RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1) 3109 RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1) 3110 RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1) --- 57 unchanged lines hidden (view full) --- 3168 STALL 3169 STALL 3170 STALL 3171 STALL 3172 STALL 3173 3174 3175 // restore all integer shadow regs | 2176 RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 2177 RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1) 2178 RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1) 2179 RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1) 2180 RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1) 2181 RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1) 2182 RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1) 2183 RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1) --- 57 unchanged lines hidden (view full) --- 2241 STALL 2242 STALL 2243 STALL 2244 STALL 2245 STALL 2246 2247 2248 // restore all integer shadow regs |
| 3176//orig#define t 8 3177//orig .repeat 7 3178//orig restore_reg \t, shadow=1 3179//orig#define t t + 1 3180//orig .endr 3181//orig restore_reg 25, shadow=1 3182//orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles 3183 | |
| 3184 RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 3185 RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 3186 RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 3187 RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 3188 RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 3189 RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 3190 RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 3191 RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 3192 RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1) 3193 3194 // 3195 // Get out of shadow mode 3196 // 3197 | 2249 RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 2250 RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 2251 RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 2252 RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 2253 RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 2254 RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 2255 RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 2256 RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 2257 RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1) 2258 2259 // 2260 // Get out of shadow mode 2261 // 2262 |
| 3198 mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig 3199 mfpr r31, pt0 // "" //orig 3200 mfpr r0, icsr // Get icsr //orig 3201//orig ldah r2, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location 3202 ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig 3203 bic r0, r2, r2 // ICSR with SDE clear //orig 3204 mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig | 2263 mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) 2264 mfpr r31, pt0 // "" 2265 mfpr r0, icsr // Get icsr 2266 ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location 2267 bic r0, r2, r2 // ICSR with SDE clear 2268 mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles |
| 3205 | 2269 |
| 3206 mfpr r31, pt0 // SDE bubble cycle 1 //orig 3207 mfpr r31, pt0 // SDE bubble cycle 2 //orig 3208 mfpr r31, pt0 // SDE bubble cycle 3 //orig 3209 nop //orig | 2270 mfpr r31, pt0 // SDE bubble cycle 1 2271 mfpr r31, pt0 // SDE bubble cycle 2 2272 mfpr r31, pt0 // SDE bubble cycle 3 2273 nop |
| 3210 | 2274 |
| 3211//orig // switch impure pointer from ipr to gpr area -- | 2275// switch impure pointer from ipr to gpr area -- |
| 3212//orig unfix_impure_ipr r1 3213//orig fix_impure_gpr r1 | 2276//orig unfix_impure_ipr r1 2277//orig fix_impure_gpr r1 |
| 3214//orig // restore all integer regs 3215//orig#define t 4 3216//orig .repeat 28 3217//orig restore_reg \t 3218//orig#define t t + 1 3219//orig .endr | |
| 3220 3221// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ... 3222 3223 lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area 3224 lda r1, 0x200(r1) // Point to center of CPU segment 3225 | 2278 2279// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ... 2280 2281 lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area 2282 lda r1, 0x200(r1) // Point to center of CPU segment 2283 |
| 2284 // restore all integer regs |
|
| 3226 RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1) 3227 RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1) 3228 RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1) 3229 RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1) 3230 RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1) 3231 RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1) 3232 RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1) 3233 RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1) --- 45 unchanged lines hidden (view full) --- 3279//orig restore_reg 0 3280//orig // restore impure area base 3281//orig unfix_impure_gpr r1 3282 3283 RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1) 3284 RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1) 3285 lda r1, -0x200(r1) // Restore impure base address 3286 | 2285 RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1) 2286 RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1) 2287 RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1) 2288 RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1) 2289 RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1) 2290 RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1) 2291 RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1) 2292 RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1) --- 45 unchanged lines hidden (view full) --- 2338//orig restore_reg 0 2339//orig // restore impure area base 2340//orig unfix_impure_gpr r1 2341 2342 RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1) 2343 RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1) 2344 lda r1, -0x200(r1) // Restore impure base address 2345 |
| 3287 mfpr r31, pt0 // stall for ldqp above //orig | 2346 mfpr r31, pt0 // stall for ldq_p above //orig |
| 3288 3289 mtpr r31, dtb_ia // clear the tb //orig 3290 mtpr r31, itb_ia // clear the itb //orig 3291 3292//orig pvc_jsr rststa, bsr=1, dest=1 3293 ret r31, (r3) // back we go //orig | 2347 2348 mtpr r31, dtb_ia // clear the tb //orig 2349 mtpr r31, itb_ia // clear the itb //orig 2350 2351//orig pvc_jsr rststa, bsr=1, dest=1 2352 ret r31, (r3) // back we go //orig |
| 3294#endif | |
| 3295 3296 | 2353 2354 |
| 3297//+ | 2355// |
| 3298// pal_pal_bug_check -- code has found a bugcheck situation. 3299// Set things up and join common machine check flow. 3300// 3301// Input: 3302// r14 - exc_addr 3303// 3304// On exit: 3305// pt0 - saved r0 3306// pt1 - saved r1 3307// pt4 - saved r4 3308// pt5 - saved r5 3309// pt6 - saved r6 3310// pt10 - saved exc_addr 3311// pt_misc<47:32> - mchk code 3312// pt_misc<31:16> - scb vector 3313// r14 - base of Cbox IPRs in IO space 3314// MCES<mchk> is set | 2356// pal_pal_bug_check -- code has found a bugcheck situation. 2357// Set things up and join common machine check flow. 2358// 2359// Input: 2360// r14 - exc_addr 2361// 2362// On exit: 2363// pt0 - saved r0 2364// pt1 - saved r1 2365// pt4 - saved r4 2366// pt5 - saved r5 2367// pt6 - saved r6 2368// pt10 - saved exc_addr 2369// pt_misc<47:32> - mchk code 2370// pt_misc<31:16> - scb vector 2371// r14 - base of Cbox IPRs in IO space 2372// MCES<mchk> is set |
| 3315//- | 2373// |
| 3316 3317 ALIGN_BLOCK 3318 .globl pal_pal_bug_check_from_int 3319pal_pal_bug_check_from_int: 3320 DEBUGSTORE(0x79) 3321//simos DEBUG_EXC_ADDR() 3322 DEBUGSTORE(0x20) 3323//simos bsr r25, put_hex --- 32 unchanged lines hidden (view full) --- 3356 mtpr r4, pt4 3357 mtpr r5, pt5 3358 3359 mtpr r6, pt6 3360 blbs r12, sys_double_machine_check // MCHK halt if double machine check 3361 3362 br r31, sys_mchk_collect_iprs // Join common machine check flow 3363 | 2374 2375 ALIGN_BLOCK 2376 .globl pal_pal_bug_check_from_int 2377pal_pal_bug_check_from_int: 2378 DEBUGSTORE(0x79) 2379//simos DEBUG_EXC_ADDR() 2380 DEBUGSTORE(0x20) 2381//simos bsr r25, put_hex --- 32 unchanged lines hidden (view full) --- 2414 mtpr r4, pt4 2415 mtpr r5, pt5 2416 2417 mtpr r6, pt6 2418 blbs r12, sys_double_machine_check // MCHK halt if double machine check 2419 2420 br r31, sys_mchk_collect_iprs // Join common machine check flow 2421 |
| 3364// align_to_call_pal_section // Align to address of first call_pal entry point - 2000 | |
| 3365 | 2422 |
| 3366// .sbttl "HALT - PALcode for HALT instruction" | |
| 3367 | 2423 |
| 3368//+ | 2424// align_to_call_pal_section 2425// Align to address of first call_pal entry point - 2000 2426 |
| 3369// | 2427// |
| 2428// HALT - PALcode for HALT instruction 2429// |
|
| 3370// Entry: 3371// Vectored into via hardware PALcode instruction dispatch. 3372// 3373// Function: 3374// GO to console code 3375// | 2430// Entry: 2431// Vectored into via hardware PALcode instruction dispatch. 2432// 2433// Function: 2434// GO to console code 2435// |
| 3376//- | 2436// |
| 3377 3378 .text 1 3379// . = 0x2000 3380 CALL_PAL_PRIV(PAL_HALT_ENTRY) 3381call_pal_halt: | 2437 2438 .text 1 2439// . = 0x2000 2440 CALL_PAL_PRIV(PAL_HALT_ENTRY) 2441call_pal_halt: |
| 3382#if rax_mode == 0 | |
| 3383 mfpr r31, pt0 // Pad exc_addr read 3384 mfpr r31, pt0 3385 3386 mfpr r12, exc_addr // get PC 3387 subq r12, 4, r12 // Point to the HALT 3388 3389 mtpr r12, exc_addr 3390 mtpr r0, pt0 3391 3392//orig pvc_jsr updpcb, bsr=1 3393 bsr r0, pal_update_pcb // update the pcb 3394 lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt 3395 br r31, sys_enter_console // enter the console 3396 | 2442 mfpr r31, pt0 // Pad exc_addr read 2443 mfpr r31, pt0 2444 2445 mfpr r12, exc_addr // get PC 2446 subq r12, 4, r12 // Point to the HALT 2447 2448 mtpr r12, exc_addr 2449 mtpr r0, pt0 2450 2451//orig pvc_jsr updpcb, bsr=1 2452 bsr r0, pal_update_pcb // update the pcb 2453 lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt 2454 br r31, sys_enter_console // enter the console 2455 |
| 3397#else // RAX mode 3398 mb 3399 mb 3400 mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles. 3401 mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles. 3402 mtpr r8, exc_addr // no HW_REI for 1 cycle. 3403 blbc r9, not_begin_case 3404 mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles. 3405 mtpr r31, ev5__itb_ia // clear ITB. 3406 3407not_begin_case: 3408 nop 3409 nop 3410 3411 nop 3412 nop // pad mt itb_asn ->hw_rei_stall 3413 3414 hw_rei_stall 3415#endif 3416 3417// .sbttl "CFLUSH- PALcode for CFLUSH instruction" 3418 3419//+ | |
| 3420// | 2456// |
| 2457// CFLUSH - PALcode for CFLUSH instruction 2458// |
|
| 3421// Entry: 3422// Vectored into via hardware PALcode instruction dispatch. 3423// 3424// R16 - contains the PFN of the page to be flushed 3425// 3426// Function: 3427// Flush all Dstream caches of 1 entire page 3428// The CFLUSH routine is in the system specific module. 3429// | 2459// Entry: 2460// Vectored into via hardware PALcode instruction dispatch. 2461// 2462// R16 - contains the PFN of the page to be flushed 2463// 2464// Function: 2465// Flush all Dstream caches of 1 entire page 2466// The CFLUSH routine is in the system specific module. 2467// |
| 3430//- | 2468// |
| 3431 3432 CALL_PAL_PRIV(PAL_CFLUSH_ENTRY) 3433Call_Pal_Cflush: 3434 br r31, sys_cflush 3435 | 2469 2470 CALL_PAL_PRIV(PAL_CFLUSH_ENTRY) 2471Call_Pal_Cflush: 2472 br r31, sys_cflush 2473 |
| 3436// .sbttl "DRAINA - PALcode for DRAINA instruction" 3437//+ | |
| 3438// | 2474// |
| 2475// DRAINA - PALcode for DRAINA instruction 2476// |
|
| 3439// Entry: 3440// Vectored into via hardware PALcode instruction dispatch. 3441// Implicit TRAPB performed by hardware. 3442// 3443// Function: 3444// Stall instruction issue until all prior instructions are guaranteed to 3445// complete without incurring aborts. For the EV5 implementation, this 3446// means waiting until all pending DREADS are returned. 3447// | 2477// Entry: 2478// Vectored into via hardware PALcode instruction dispatch. 2479// Implicit TRAPB performed by hardware. 2480// 2481// Function: 2482// Stall instruction issue until all prior instructions are guaranteed to 2483// complete without incurring aborts. For the EV5 implementation, this 2484// means waiting until all pending DREADS are returned. 2485// |
| 3448//- | 2486// |
| 3449 3450 CALL_PAL_PRIV(PAL_DRAINA_ENTRY) 3451Call_Pal_Draina: 3452 ldah r14, 0x100(r31) // Init counter. Value? 3453 nop 3454 3455DRAINA_LOOP: 3456 subq r14, 1, r14 // Decrement counter --- 5 unchanged lines hidden (view full) --- 3462 nop 3463 blbs r13, DRAINA_LOOP // Wait until all DREADS clear 3464 3465 hw_rei 3466 3467DRAINA_LOOP_TOO_LONG: 3468 br r31, call_pal_halt 3469 | 2487 2488 CALL_PAL_PRIV(PAL_DRAINA_ENTRY) 2489Call_Pal_Draina: 2490 ldah r14, 0x100(r31) // Init counter. Value? 2491 nop 2492 2493DRAINA_LOOP: 2494 subq r14, 1, r14 // Decrement counter --- 5 unchanged lines hidden (view full) --- 2500 nop 2501 blbs r13, DRAINA_LOOP // Wait until all DREADS clear 2502 2503 hw_rei 2504 2505DRAINA_LOOP_TOO_LONG: 2506 br r31, call_pal_halt 2507 |
| 3470// .sbttl "CALL_PAL OPCDECs" | 2508// CALL_PAL OPCDECs |
| 3471 3472 CALL_PAL_PRIV(0x0003) 3473CallPal_OpcDec03: 3474 br r31, osfpal_calpal_opcdec 3475 3476 CALL_PAL_PRIV(0x0004) 3477CallPal_OpcDec04: 3478 br r31, osfpal_calpal_opcdec --- 9 unchanged lines hidden (view full) --- 3488 CALL_PAL_PRIV(0x0007) 3489CallPal_OpcDec07: 3490 br r31, osfpal_calpal_opcdec 3491 3492 CALL_PAL_PRIV(0x0008) 3493CallPal_OpcDec08: 3494 br r31, osfpal_calpal_opcdec 3495 | 2509 2510 CALL_PAL_PRIV(0x0003) 2511CallPal_OpcDec03: 2512 br r31, osfpal_calpal_opcdec 2513 2514 CALL_PAL_PRIV(0x0004) 2515CallPal_OpcDec04: 2516 br r31, osfpal_calpal_opcdec --- 9 unchanged lines hidden (view full) --- 2526 CALL_PAL_PRIV(0x0007) 2527CallPal_OpcDec07: 2528 br r31, osfpal_calpal_opcdec 2529 2530 CALL_PAL_PRIV(0x0008) 2531CallPal_OpcDec08: 2532 br r31, osfpal_calpal_opcdec 2533 |
| 3496// .sbttl "CSERVE- PALcode for CSERVE instruction" 3497//+ | |
| 3498// | 2534// |
| 2535// CSERVE - PALcode for CSERVE instruction 2536// |
|
| 3499// Entry: 3500// Vectored into via hardware PALcode instruction dispatch. 3501// 3502// Function: 3503// Various functions for private use of console software 3504// 3505// option selector in r0 3506// arguments in r16.... 3507// The CSERVE routine is in the system specific module. 3508// | 2537// Entry: 2538// Vectored into via hardware PALcode instruction dispatch. 2539// 2540// Function: 2541// Various functions for private use of console software 2542// 2543// option selector in r0 2544// arguments in r16.... 2545// The CSERVE routine is in the system specific module. 2546// |
| 3509//- | 2547// |
| 3510 3511 CALL_PAL_PRIV(PAL_CSERVE_ENTRY) 3512Call_Pal_Cserve: 3513 br r31, sys_cserve 3514 | 2548 2549 CALL_PAL_PRIV(PAL_CSERVE_ENTRY) 2550Call_Pal_Cserve: 2551 br r31, sys_cserve 2552 |
| 3515// .sbttl "swppal - PALcode for swppal instruction" 3516 3517//+ | |
| 3518// | 2553// |
| 2554// swppal - PALcode for swppal instruction 2555// |
|
| 3519// Entry: 3520// Vectored into via hardware PALcode instruction dispatch. 3521// Vectored into via hardware PALcode instruction dispatch. 3522// R16 contains the new PAL identifier 3523// R17:R21 contain implementation-specific entry parameters 3524// 3525// R0 receives status: 3526// 0 success (PAL was switched) 3527// 1 unknown PAL variant 3528// 2 known PAL variant, but PAL not loaded 3529// 3530// 3531// Function: 3532// Swap control to another PAL. | 2556// Entry: 2557// Vectored into via hardware PALcode instruction dispatch. 2558// Vectored into via hardware PALcode instruction dispatch. 2559// R16 contains the new PAL identifier 2560// R17:R21 contain implementation-specific entry parameters 2561// 2562// R0 receives status: 2563// 0 success (PAL was switched) 2564// 1 unknown PAL variant 2565// 2 known PAL variant, but PAL not loaded 2566// 2567// 2568// Function: 2569// Swap control to another PAL. |
| 3533//- | 2570// |
| 3534 3535 CALL_PAL_PRIV(PAL_SWPPAL_ENTRY) 3536Call_Pal_Swppal: 3537 cmpule r16, 255, r0 // see if a kibble was passed 3538 cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59) 3539 3540 or r16, r31, r3 // set r3 incase this is a address 3541 blbc r0, swppal_cont // nope, try it as an address --- 4 unchanged lines hidden (view full) --- 3546 br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF 3547 3548// .global osfpal_hw_entry_reset 3549// .weak osfpal_hw_entry_reset 3550// .long <osfpal_hw_entry_reset-pal_start> 3551//orig halt // don't know how to get the address here - kludge ok, load pal at 0 3552 .long 0 // ?? hack upon hack...pb 3553 | 2571 2572 CALL_PAL_PRIV(PAL_SWPPAL_ENTRY) 2573Call_Pal_Swppal: 2574 cmpule r16, 255, r0 // see if a kibble was passed 2575 cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59) 2576 2577 or r16, r31, r3 // set r3 incase this is a address 2578 blbc r0, swppal_cont // nope, try it as an address --- 4 unchanged lines hidden (view full) --- 2583 br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF 2584 2585// .global osfpal_hw_entry_reset 2586// .weak osfpal_hw_entry_reset 2587// .long <osfpal_hw_entry_reset-pal_start> 2588//orig halt // don't know how to get the address here - kludge ok, load pal at 0 2589 .long 0 // ?? hack upon hack...pb 2590 |
| 3554CALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr | 2591CALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr |
| 3555// ble r3, swppal_fail ; if OSF not linked in say not loaded. 3556 mfpr r2, pal_base // fetch pal base 3557 3558 addq r2, r3, r3 // add pal base 3559 lda r2, 0x3FFF(r31) // get pal base checker mask 3560 3561 and r3, r2, r2 // any funky bits set? 3562 cmpeq r2, 0, r0 // --- 6 unchanged lines hidden (view full) --- 3569 CALL_PAL_PRIV(0x000B) 3570CallPal_OpcDec0B: 3571 br r31, osfpal_calpal_opcdec 3572 3573 CALL_PAL_PRIV(0x000C) 3574CallPal_OpcDec0C: 3575 br r31, osfpal_calpal_opcdec 3576 | 2592// ble r3, swppal_fail ; if OSF not linked in say not loaded. 2593 mfpr r2, pal_base // fetch pal base 2594 2595 addq r2, r3, r3 // add pal base 2596 lda r2, 0x3FFF(r31) // get pal base checker mask 2597 2598 and r3, r2, r2 // any funky bits set? 2599 cmpeq r2, 0, r0 // --- 6 unchanged lines hidden (view full) --- 2606 CALL_PAL_PRIV(0x000B) 2607CallPal_OpcDec0B: 2608 br r31, osfpal_calpal_opcdec 2609 2610 CALL_PAL_PRIV(0x000C) 2611CallPal_OpcDec0C: 2612 br r31, osfpal_calpal_opcdec 2613 |
| 3577// .sbttl "wripir- PALcode for wripir instruction" 3578//+ | |
| 3579// | 2614// |
| 2615// wripir - PALcode for wripir instruction 2616// |
|
| 3580// Entry: 3581// Vectored into via hardware PALcode instruction dispatch. 3582// r16 = processor number to interrupt 3583// 3584// Function: 3585// IPIR <- R16 3586// Handled in system-specific code 3587// 3588// Exit: 3589// interprocessor interrupt is recorded on the target processor 3590// and is initiated when the proper enabling conditions are present. | 2617// Entry: 2618// Vectored into via hardware PALcode instruction dispatch. 2619// r16 = processor number to interrupt 2620// 2621// Function: 2622// IPIR <- R16 2623// Handled in system-specific code 2624// 2625// Exit: 2626// interprocessor interrupt is recorded on the target processor 2627// and is initiated when the proper enabling conditions are present. |
| 3591//- | 2628// |
| 3592 3593 CALL_PAL_PRIV(PAL_WRIPIR_ENTRY) 3594Call_Pal_Wrpir: 3595 br r31, sys_wripir 3596 3597// .sbttl "CALL_PAL OPCDECs" 3598 3599 CALL_PAL_PRIV(0x000E) 3600CallPal_OpcDec0E: 3601 br r31, osfpal_calpal_opcdec 3602 3603 CALL_PAL_PRIV(0x000F) 3604CallPal_OpcDec0F: 3605 br r31, osfpal_calpal_opcdec 3606 | 2629 2630 CALL_PAL_PRIV(PAL_WRIPIR_ENTRY) 2631Call_Pal_Wrpir: 2632 br r31, sys_wripir 2633 2634// .sbttl "CALL_PAL OPCDECs" 2635 2636 CALL_PAL_PRIV(0x000E) 2637CallPal_OpcDec0E: 2638 br r31, osfpal_calpal_opcdec 2639 2640 CALL_PAL_PRIV(0x000F) 2641CallPal_OpcDec0F: 2642 br r31, osfpal_calpal_opcdec 2643 |
| 3607// .sbttl "rdmces- PALcode for rdmces instruction" 3608 3609//+ | |
| 3610// | 2644// |
| 2645// rdmces - PALcode for rdmces instruction 2646// |
|
| 3611// Entry: 3612// Vectored into via hardware PALcode instruction dispatch. 3613// 3614// Function: 3615// R0 <- ZEXT(MCES) | 2647// Entry: 2648// Vectored into via hardware PALcode instruction dispatch. 2649// 2650// Function: 2651// R0 <- ZEXT(MCES) |
| 3616//- | 2652// |
| 3617 3618 CALL_PAL_PRIV(PAL_RDMCES_ENTRY) 3619Call_Pal_Rdmces: 3620 mfpr r0, pt_mces // Read from PALtemp 3621 and r0, mces_m_all, r0 // Clear other bits 3622 3623 hw_rei 3624 | 2653 2654 CALL_PAL_PRIV(PAL_RDMCES_ENTRY) 2655Call_Pal_Rdmces: 2656 mfpr r0, pt_mces // Read from PALtemp 2657 and r0, mces_m_all, r0 // Clear other bits 2658 2659 hw_rei 2660 |
| 3625// .sbttl "wrmces- PALcode for wrmces instruction" 3626 3627//+ | |
| 3628// | 2661// |
| 2662// wrmces - PALcode for wrmces instruction 2663// |
|
| 3629// Entry: 3630// Vectored into via hardware PALcode instruction dispatch. 3631// 3632// Function: 3633// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK) 3634// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE) 3635// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE) 3636// MCES<3> <- R16<3> (DPC) 3637// MCES<4> <- R16<4> (DSC) 3638// | 2664// Entry: 2665// Vectored into via hardware PALcode instruction dispatch. 2666// 2667// Function: 2668// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK) 2669// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE) 2670// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE) 2671// MCES<3> <- R16<3> (DPC) 2672// MCES<4> <- R16<4> (DSC) 2673// |
| 3639//- | 2674// |
| 3640 3641 CALL_PAL_PRIV(PAL_WRMCES_ENTRY) 3642Call_Pal_Wrmces: 3643 and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE 3644 mfpr r14, pt_mces // Get current value 3645 3646 ornot r31, r13, r13 // Flip all the bits 3647 and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17 3648 3649 and r14, r13, r1 // Update MCHK, SCE, PCE 3650 bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC 3651 3652 or r1, r17, r1 // Update DPC and DSC 3653 mtpr r1, pt_mces // Write MCES back 3654 | 2675 2676 CALL_PAL_PRIV(PAL_WRMCES_ENTRY) 2677Call_Pal_Wrmces: 2678 and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE 2679 mfpr r14, pt_mces // Get current value 2680 2681 ornot r31, r13, r13 // Flip all the bits 2682 and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17 2683 2684 and r14, r13, r1 // Update MCHK, SCE, PCE 2685 bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC 2686 2687 or r1, r17, r1 // Update DPC and DSC 2688 mtpr r1, pt_mces // Write MCES back 2689 |
| 3655#if rawhide_system == 0 | |
| 3656 nop // Pad to fix PT write->read restriction | 2690 nop // Pad to fix PT write->read restriction |
| 3657#else 3658 blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock 3659#endif | |
| 3660 3661 nop 3662 hw_rei 3663 3664 3665 | 2691 2692 nop 2693 hw_rei 2694 2695 2696 |
| 3666// .sbttl "CALL_PAL OPCDECs" | 2697// CALL_PAL OPCDECs |
| 3667 3668 CALL_PAL_PRIV(0x0012) 3669CallPal_OpcDec12: 3670 br r31, osfpal_calpal_opcdec 3671 3672 CALL_PAL_PRIV(0x0013) 3673CallPal_OpcDec13: 3674 br r31, osfpal_calpal_opcdec --- 85 unchanged lines hidden (view full) --- 3760 CALL_PAL_PRIV(0x0029) 3761CallPal_OpcDec29: 3762 br r31, osfpal_calpal_opcdec 3763 3764 CALL_PAL_PRIV(0x002A) 3765CallPal_OpcDec2A: 3766 br r31, osfpal_calpal_opcdec 3767 | 2698 2699 CALL_PAL_PRIV(0x0012) 2700CallPal_OpcDec12: 2701 br r31, osfpal_calpal_opcdec 2702 2703 CALL_PAL_PRIV(0x0013) 2704CallPal_OpcDec13: 2705 br r31, osfpal_calpal_opcdec --- 85 unchanged lines hidden (view full) --- 2791 CALL_PAL_PRIV(0x0029) 2792CallPal_OpcDec29: 2793 br r31, osfpal_calpal_opcdec 2794 2795 CALL_PAL_PRIV(0x002A) 2796CallPal_OpcDec2A: 2797 br r31, osfpal_calpal_opcdec 2798 |
| 3768// .sbttl "wrfen - PALcode for wrfen instruction" 3769 3770//+ | |
| 3771// | 2799// |
| 2800// wrfen - PALcode for wrfen instruction 2801// |
|
| 3772// Entry: 3773// Vectored into via hardware PALcode instruction dispatch. 3774// 3775// Function: 3776// a0<0> -> ICSR<FPE> 3777// Store new FEN in PCB | 2802// Entry: 2803// Vectored into via hardware PALcode instruction dispatch. 2804// 2805// Function: 2806// a0<0> -> ICSR<FPE> 2807// Store new FEN in PCB |
| 3778// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE | 2808// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) 2809// are UNPREDICTABLE |
| 3779// 3780// Issue: What about pending FP loads when FEN goes from on->off???? | 2810// 2811// Issue: What about pending FP loads when FEN goes from on->off???? |
| 3781//- | 2812// |
| 3782 3783 CALL_PAL_PRIV(PAL_WRFEN_ENTRY) 3784Call_Pal_Wrfen: 3785 or r31, 1, r13 // Get a one 3786 mfpr r1, ev5__icsr // Get current FPE 3787 3788 sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0 3789 and r16, 1, r16 // clean new fen 3790 3791 sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position 3792 bic r1, r13, r1 // zero icsr<fpe> 3793 3794 or r1, r12, r1 // Or new FEN into ICSR 3795 mfpr r12, pt_pcbb // Get PCBB - E1 3796 3797 mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI | 2813 2814 CALL_PAL_PRIV(PAL_WRFEN_ENTRY) 2815Call_Pal_Wrfen: 2816 or r31, 1, r13 // Get a one 2817 mfpr r1, ev5__icsr // Get current FPE 2818 2819 sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0 2820 and r16, 1, r16 // clean new fen 2821 2822 sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position 2823 bic r1, r13, r1 // zero icsr<fpe> 2824 2825 or r1, r12, r1 // Or new FEN into ICSR 2826 mfpr r12, pt_pcbb // Get PCBB - E1 2827 2828 mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI |
| 3798 stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB. | 2829 stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB. |
| 3799 3800 mfpr r31, pt0 // Pad ICSR<FPE> write. 3801 mfpr r31, pt0 3802 3803 mfpr r31, pt0 3804// pvc_violate 225 // cuz PVC can't distinguish which bits changed 3805 hw_rei 3806 3807 3808 CALL_PAL_PRIV(0x002C) 3809CallPal_OpcDec2C: 3810 br r31, osfpal_calpal_opcdec 3811 | 2830 2831 mfpr r31, pt0 // Pad ICSR<FPE> write. 2832 mfpr r31, pt0 2833 2834 mfpr r31, pt0 2835// pvc_violate 225 // cuz PVC can't distinguish which bits changed 2836 hw_rei 2837 2838 2839 CALL_PAL_PRIV(0x002C) 2840CallPal_OpcDec2C: 2841 br r31, osfpal_calpal_opcdec 2842 |
| 3812// .sbttl "wrvptpr - PALcode for wrvptpr instruction" 3813//+ | |
| 3814// | 2843// |
| 2844// wrvptpr - PALcode for wrvptpr instruction 2845// |
|
| 3815// Entry: 3816// Vectored into via hardware PALcode instruction dispatch. 3817// 3818// Function: 3819// vptptr <- a0 (r16) | 2846// Entry: 2847// Vectored into via hardware PALcode instruction dispatch. 2848// 2849// Function: 2850// vptptr <- a0 (r16) |
| 3820//- | 2851// |
| 3821 3822 CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY) 3823Call_Pal_Wrvptptr: 3824 mtpr r16, ev5__mvptbr // Load Mbox copy 3825 mtpr r16, ev5__ivptbr // Load Ibox copy 3826 nop // Pad IPR write 3827 nop 3828 hw_rei 3829 3830 CALL_PAL_PRIV(0x002E) 3831CallPal_OpcDec2E: 3832 br r31, osfpal_calpal_opcdec 3833 3834 CALL_PAL_PRIV(0x002F) 3835CallPal_OpcDec2F: 3836 br r31, osfpal_calpal_opcdec 3837 | 2852 2853 CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY) 2854Call_Pal_Wrvptptr: 2855 mtpr r16, ev5__mvptbr // Load Mbox copy 2856 mtpr r16, ev5__ivptbr // Load Ibox copy 2857 nop // Pad IPR write 2858 nop 2859 hw_rei 2860 2861 CALL_PAL_PRIV(0x002E) 2862CallPal_OpcDec2E: 2863 br r31, osfpal_calpal_opcdec 2864 2865 CALL_PAL_PRIV(0x002F) 2866CallPal_OpcDec2F: 2867 br r31, osfpal_calpal_opcdec 2868 |
| 3838// .sbttl "swpctx- PALcode for swpctx instruction" | |
| 3839 | 2869 |
| 3840//+ | |
| 3841// | 2870// |
| 2871// swpctx - PALcode for swpctx instruction 2872// |
|
| 3842// Entry: 3843// hardware dispatch via callPal instruction 3844// R16 -> new pcb 3845// 3846// Function: 3847// dynamic state moved to old pcb 3848// new state loaded from new pcb 3849// pcbb pointer set 3850// old pcbb returned in R0 3851// 3852// Note: need to add perf monitor stuff | 2873// Entry: 2874// hardware dispatch via callPal instruction 2875// R16 -> new pcb 2876// 2877// Function: 2878// dynamic state moved to old pcb 2879// new state loaded from new pcb 2880// pcbb pointer set 2881// old pcbb returned in R0 2882// 2883// Note: need to add perf monitor stuff |
| 3853//- | 2884// |
| 3854 3855 CALL_PAL_PRIV(PAL_SWPCTX_ENTRY) 3856Call_Pal_Swpctx: 3857 rpcc r13 // get cyccounter 3858 mfpr r0, pt_pcbb // get pcbb 3859 | 2885 2886 CALL_PAL_PRIV(PAL_SWPCTX_ENTRY) 2887Call_Pal_Swpctx: 2888 rpcc r13 // get cyccounter 2889 mfpr r0, pt_pcbb // get pcbb 2890 |
| 3860 ldqp r22, osfpcb_q_fen(r16) // get new fen/pme 3861 ldqp r23, osfpcb_l_cc(r16) // get new asn | 2891 ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme 2892 ldq_p r23, osfpcb_l_cc(r16) // get new asn |
| 3862 3863 srl r13, 32, r25 // move offset 3864 mfpr r24, pt_usp // get usp 3865 | 2893 2894 srl r13, 32, r25 // move offset 2895 mfpr r24, pt_usp // get usp 2896 |
| 3866 stqp r30, osfpcb_q_ksp(r0) // store old ksp 3867// pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow. | 2897 stq_p r30, osfpcb_q_ksp(r0) // store old ksp 2898// pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow. |
| 3868 mtpr r16, pt_pcbb // set new pcbb 3869 | 2899 mtpr r16, pt_pcbb // set new pcbb 2900 |
| 3870 stqp r24, osfpcb_q_usp(r0) // store usp | 2901 stq_p r24, osfpcb_q_usp(r0) // store usp |
| 3871 addl r13, r25, r25 // merge for new time 3872 | 2902 addl r13, r25, r25 // merge for new time 2903 |
| 3873 stlp r25, osfpcb_l_cc(r0) // save time | 2904 stl_p r25, osfpcb_l_cc(r0) // save time |
| 3874 ldah r24, (1<<(icsr_v_fpe-16))(r31) 3875 3876 and r22, 1, r12 // isolate fen 3877 mfpr r25, icsr // get current icsr 3878 | 2905 ldah r24, (1<<(icsr_v_fpe-16))(r31) 2906 2907 and r22, 1, r12 // isolate fen 2908 mfpr r25, icsr // get current icsr 2909 |
| 3879 ev5_pass2 lda r24, (1<<icsr_v_pmp)(r24) | 2910 lda r24, (1< |
| 3880 br r31, swpctx_cont 3881 | 2911 br r31, swpctx_cont 2912 |
| 3882// .sbttl "wrval - PALcode for wrval instruction" 3883//+ | |
| 3884// | 2913// |
| 2914// wrval - PALcode for wrval instruction 2915// |
|
| 3885// Entry: 3886// Vectored into via hardware PALcode instruction dispatch. 3887// 3888// Function: 3889// sysvalue <- a0 (r16) | 2916// Entry: 2917// Vectored into via hardware PALcode instruction dispatch. 2918// 2919// Function: 2920// sysvalue <- a0 (r16) |
| 3890//- | 2921// |
| 3891 3892 CALL_PAL_PRIV(PAL_WRVAL_ENTRY) 3893Call_Pal_Wrval: 3894 nop 3895 mtpr r16, pt_sysval // Pad paltemp write 3896 nop 3897 nop 3898 hw_rei 3899 | 2922 2923 CALL_PAL_PRIV(PAL_WRVAL_ENTRY) 2924Call_Pal_Wrval: 2925 nop 2926 mtpr r16, pt_sysval // Pad paltemp write 2927 nop 2928 nop 2929 hw_rei 2930 |
| 3900 3901// .sbttl "rdval - PALcode for rdval instruction" 3902 3903//+ | |
| 3904// | 2931// |
| 2932// rdval - PALcode for rdval instruction 2933// |
|
| 3905// Entry: 3906// Vectored into via hardware PALcode instruction dispatch. 3907// 3908// Function: 3909// v0 (r0) <- sysvalue | 2934// Entry: 2935// Vectored into via hardware PALcode instruction dispatch. 2936// 2937// Function: 2938// v0 (r0) <- sysvalue |
| 3910//- | 2939// |
| 3911 3912 CALL_PAL_PRIV(PAL_RDVAL_ENTRY) 3913Call_Pal_Rdval: 3914 nop 3915 mfpr r0, pt_sysval 3916 nop 3917 hw_rei 3918 | 2940 2941 CALL_PAL_PRIV(PAL_RDVAL_ENTRY) 2942Call_Pal_Rdval: 2943 nop 2944 mfpr r0, pt_sysval 2945 nop 2946 hw_rei 2947 |
| 3919// .sbttl "tbi - PALcode for tbi instruction" 3920//+ | |
| 3921// | 2948// |
| 2949// tbi - PALcode for tbi instruction 2950// |
|
| 3922// Entry: 3923// Vectored into via hardware PALcode instruction dispatch. 3924// 3925// Function: 3926// TB invalidate 3927// r16/a0 = TBI type 3928// r17/a1 = Va for TBISx instructions | 2951// Entry: 2952// Vectored into via hardware PALcode instruction dispatch. 2953// 2954// Function: 2955// TB invalidate 2956// r16/a0 = TBI type 2957// r17/a1 = Va for TBISx instructions |
| 3929//- | 2958// |
| 3930 3931 CALL_PAL_PRIV(PAL_TBI_ENTRY) 3932Call_Pal_Tbi: 3933 addq r16, 2, r16 // change range to 0-2 3934 br r23, CALL_PAL_tbi_10_ // get our address 3935 3936CALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range 3937 lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table 3938 sll r16, 4, r16 // * 16 3939 blbc r22, CALL_PAL_tbi_30_ // go rei, if not 3940 3941 addq r23, r16, r23 // addr of our code 3942//orig pvc_jsr tbi 3943 jmp r31, (r23) // and go do it 3944 3945CALL_PAL_tbi_30_: 3946 hw_rei 3947 nop 3948 | 2959 2960 CALL_PAL_PRIV(PAL_TBI_ENTRY) 2961Call_Pal_Tbi: 2962 addq r16, 2, r16 // change range to 0-2 2963 br r23, CALL_PAL_tbi_10_ // get our address 2964 2965CALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range 2966 lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table 2967 sll r16, 4, r16 // * 16 2968 blbc r22, CALL_PAL_tbi_30_ // go rei, if not 2969 2970 addq r23, r16, r23 // addr of our code 2971//orig pvc_jsr tbi 2972 jmp r31, (r23) // and go do it 2973 2974CALL_PAL_tbi_30_: 2975 hw_rei 2976 nop 2977 |
| 3949// .sbttl "wrent - PALcode for wrent instruction" 3950//+ | |
| 3951// | 2978// |
| 2979// wrent - PALcode for wrent instruction 2980// |
|
| 3952// Entry: 3953// Vectored into via hardware PALcode instruction dispatch. 3954// 3955// Function: 3956// Update ent* in paltemps 3957// r16/a0 = Address of entry routine 3958// r17/a1 = Entry Number 0..5 3959// 3960// r22, r23 trashed | 2981// Entry: 2982// Vectored into via hardware PALcode instruction dispatch. 2983// 2984// Function: 2985// Update ent* in paltemps 2986// r16/a0 = Address of entry routine 2987// r17/a1 = Entry Number 0..5 2988// 2989// r22, r23 trashed |
| 3961//- | 2990// |
| 3962 3963 CALL_PAL_PRIV(PAL_WRENT_ENTRY) 3964Call_Pal_Wrent: 3965 cmpult r17, 6, r22 // see if in range 3966 br r23, CALL_PAL_wrent_10_ // get our address 3967 3968CALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc 3969 blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range 3970 3971 lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table 3972 sll r17, 4, r17 // *16 3973 3974 addq r17, r23, r23 // Get address in table 3975//orig pvc_jsr wrent 3976 jmp r31, (r23) // and go do it 3977 3978CALL_PAL_wrent_30_: 3979 hw_rei // out of range, just return 3980 | 2991 2992 CALL_PAL_PRIV(PAL_WRENT_ENTRY) 2993Call_Pal_Wrent: 2994 cmpult r17, 6, r22 // see if in range 2995 br r23, CALL_PAL_wrent_10_ // get our address 2996 2997CALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc 2998 blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range 2999 3000 lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table 3001 sll r17, 4, r17 // *16 3002 3003 addq r17, r23, r23 // Get address in table 3004//orig pvc_jsr wrent 3005 jmp r31, (r23) // and go do it 3006 3007CALL_PAL_wrent_30_: 3008 hw_rei // out of range, just return 3009 |
| 3981// .sbttl "swpipl - PALcode for swpipl instruction" 3982//+ | |
| 3983// | 3010// |
| 3011// swpipl - PALcode for swpipl instruction 3012// |
|
| 3984// Entry: 3985// Vectored into via hardware PALcode instruction dispatch. 3986// 3987// Function: 3988// v0 (r0) <- PS<IPL> 3989// PS<IPL> <- a0<2:0> (r16) 3990// 3991// t8 (r22) is scratch | 3013// Entry: 3014// Vectored into via hardware PALcode instruction dispatch. 3015// 3016// Function: 3017// v0 (r0) <- PS<IPL> 3018// PS<IPL> <- a0<2:0> (r16) 3019// 3020// t8 (r22) is scratch |
| 3992//- | 3021// |
| 3993 3994 CALL_PAL_PRIV(PAL_SWPIPL_ENTRY) 3995Call_Pal_Swpipl: 3996 and r16, osfps_m_ipl, r16 // clean New ipl 3997 mfpr r22, pt_intmask // get int mask 3998 3999 extbl r22, r16, r22 // get mask for this ipl 4000 bis r11, r31, r0 // return old ipl 4001 4002 bis r16, r31, r11 // set new ps 4003 mtpr r22, ev5__ipl // set new mask 4004 4005 mfpr r31, pt0 // pad ipl write 4006 mfpr r31, pt0 // pad ipl write 4007 4008 hw_rei // back 4009 | 3022 3023 CALL_PAL_PRIV(PAL_SWPIPL_ENTRY) 3024Call_Pal_Swpipl: 3025 and r16, osfps_m_ipl, r16 // clean New ipl 3026 mfpr r22, pt_intmask // get int mask 3027 3028 extbl r22, r16, r22 // get mask for this ipl 3029 bis r11, r31, r0 // return old ipl 3030 3031 bis r16, r31, r11 // set new ps 3032 mtpr r22, ev5__ipl // set new mask 3033 3034 mfpr r31, pt0 // pad ipl write 3035 mfpr r31, pt0 // pad ipl write 3036 3037 hw_rei // back 3038 |
| 4010// .sbttl "rdps - PALcode for rdps instruction" 4011//+ | |
| 4012// | 3039// |
| 3040// rdps - PALcode for rdps instruction 3041// |
|
| 4013// Entry: 4014// Vectored into via hardware PALcode instruction dispatch. 4015// 4016// Function: 4017// v0 (r0) <- ps | 3042// Entry: 3043// Vectored into via hardware PALcode instruction dispatch. 3044// 3045// Function: 3046// v0 (r0) <- ps |
| 4018//- | 3047// |
| 4019 4020 CALL_PAL_PRIV(PAL_RDPS_ENTRY) 4021Call_Pal_Rdps: 4022 bis r11, r31, r0 // Fetch PALshadow PS 4023 nop // Must be 2 cycles long 4024 hw_rei 4025 | 3048 3049 CALL_PAL_PRIV(PAL_RDPS_ENTRY) 3050Call_Pal_Rdps: 3051 bis r11, r31, r0 // Fetch PALshadow PS 3052 nop // Must be 2 cycles long 3053 hw_rei 3054 |
| 4026// .sbttl "wrkgp - PALcode for wrkgp instruction" 4027//+ | |
| 4028// | 3055// |
| 3056// wrkgp - PALcode for wrkgp instruction 3057// |
|
| 4029// Entry: 4030// Vectored into via hardware PALcode instruction dispatch. 4031// 4032// Function: 4033// kgp <- a0 (r16) | 3058// Entry: 3059// Vectored into via hardware PALcode instruction dispatch. 3060// 3061// Function: 3062// kgp <- a0 (r16) |
| 4034//- | 3063// |
| 4035 4036 CALL_PAL_PRIV(PAL_WRKGP_ENTRY) 4037Call_Pal_Wrkgp: 4038 nop 4039 mtpr r16, pt_kgp 4040 nop // Pad for pt write->read restriction 4041 nop 4042 hw_rei 4043 | 3064 3065 CALL_PAL_PRIV(PAL_WRKGP_ENTRY) 3066Call_Pal_Wrkgp: 3067 nop 3068 mtpr r16, pt_kgp 3069 nop // Pad for pt write->read restriction 3070 nop 3071 hw_rei 3072 |
| 4044// .sbttl "wrusp - PALcode for wrusp instruction" 4045//+ | |
| 4046// | 3073// |
| 3074// wrusp - PALcode for wrusp instruction 3075// |
|
| 4047// Entry: 4048// Vectored into via hardware PALcode instruction dispatch. 4049// 4050// Function: 4051// usp <- a0 (r16) | 3076// Entry: 3077// Vectored into via hardware PALcode instruction dispatch. 3078// 3079// Function: 3080// usp <- a0 (r16) |
| 4052//- | 3081// |
| 4053 4054 CALL_PAL_PRIV(PAL_WRUSP_ENTRY) 4055Call_Pal_Wrusp: 4056 nop 4057 mtpr r16, pt_usp 4058 nop // Pad possible pt write->read restriction 4059 nop 4060 hw_rei 4061 | 3082 3083 CALL_PAL_PRIV(PAL_WRUSP_ENTRY) 3084Call_Pal_Wrusp: 3085 nop 3086 mtpr r16, pt_usp 3087 nop // Pad possible pt write->read restriction 3088 nop 3089 hw_rei 3090 |
| 4062// .sbttl "wrperfmon - PALcode for wrperfmon instruction" 4063//+ | |
| 4064// | 3091// |
| 3092// wrperfmon - PALcode for wrperfmon instruction 3093// |
|
| 4065// Entry: 4066// Vectored into via hardware PALcode instruction dispatch. 4067// 4068// 4069// Function: 4070// Various control functions for the onchip performance counters 4071// 4072// option selector in r16 --- 59 unchanged lines hidden (view full) --- 4132// 1 1 frequency = 256 4133// note: FRQx<1:0> = 00 will keep counters from ever being enabled. 4134// 4135//============================================================================= 4136// 4137 CALL_PAL_PRIV(0x0039) 4138// unsupported in Hudson code .. pboyle Nov/95 4139CALL_PAL_Wrperfmon: | 3094// Entry: 3095// Vectored into via hardware PALcode instruction dispatch. 3096// 3097// 3098// Function: 3099// Various control functions for the onchip performance counters 3100// 3101// option selector in r16 --- 59 unchanged lines hidden (view full) --- 3161// 1 1 frequency = 256 3162// note: FRQx<1:0> = 00 will keep counters from ever being enabled. 3163// 3164//============================================================================= 3165// 3166 CALL_PAL_PRIV(0x0039) 3167// unsupported in Hudson code .. pboyle Nov/95 3168CALL_PAL_Wrperfmon: |
| 4140#if perfmon_debug == 0 | |
| 4141 // "real" performance monitoring code 4142 cmpeq r16, 1, r0 // check for enable 4143 bne r0, perfmon_en // br if requested to enable 4144 4145 cmpeq r16, 2, r0 // check for mux ctl 4146 bne r0, perfmon_muxctl // br if request to set mux controls 4147 4148 cmpeq r16, 3, r0 // check for options --- 8 unchanged lines hidden (view full) --- 4157 cmpeq r16, 6, r0 // check for counter write request 4158 bne r0, perfmon_wr // br if request to write counters 4159 4160 cmpeq r16, 7, r0 // check for counter clear/enable request 4161 bne r0, perfmon_enclr // br if request to clear/enable counters 4162 4163 beq r16, perfmon_dis // br if requested to disable (r16=0) 4164 br r31, perfmon_unknown // br if unknown request | 3169 // "real" performance monitoring code 3170 cmpeq r16, 1, r0 // check for enable 3171 bne r0, perfmon_en // br if requested to enable 3172 3173 cmpeq r16, 2, r0 // check for mux ctl 3174 bne r0, perfmon_muxctl // br if request to set mux controls 3175 3176 cmpeq r16, 3, r0 // check for options --- 8 unchanged lines hidden (view full) --- 3185 cmpeq r16, 6, r0 // check for counter write request 3186 bne r0, perfmon_wr // br if request to write counters 3187 3188 cmpeq r16, 7, r0 // check for counter clear/enable request 3189 bne r0, perfmon_enclr // br if request to clear/enable counters 3190 3191 beq r16, perfmon_dis // br if requested to disable (r16=0) 3192 br r31, perfmon_unknown // br if unknown request |
| 4165#else | |
| 4166 | 3193 |
| 4167 br r31, pal_perfmon_debug 4168#endif 4169 4170// .sbttl "rdusp - PALcode for rdusp instruction" 4171//+ | |
| 4172// | 3194// |
| 3195// rdusp - PALcode for rdusp instruction 3196// |
|
| 4173// Entry: 4174// Vectored into via hardware PALcode instruction dispatch. 4175// 4176// Function: 4177// v0 (r0) <- usp | 3197// Entry: 3198// Vectored into via hardware PALcode instruction dispatch. 3199// 3200// Function: 3201// v0 (r0) <- usp |
| 4178//- | 3202// |
| 4179 4180 CALL_PAL_PRIV(PAL_RDUSP_ENTRY) 4181Call_Pal_Rdusp: 4182 nop 4183 mfpr r0, pt_usp 4184 hw_rei 4185 4186 4187 CALL_PAL_PRIV(0x003B) 4188CallPal_OpcDec3B: 4189 br r31, osfpal_calpal_opcdec 4190 | 3203 3204 CALL_PAL_PRIV(PAL_RDUSP_ENTRY) 3205Call_Pal_Rdusp: 3206 nop 3207 mfpr r0, pt_usp 3208 hw_rei 3209 3210 3211 CALL_PAL_PRIV(0x003B) 3212CallPal_OpcDec3B: 3213 br r31, osfpal_calpal_opcdec 3214 |
| 4191// .sbttl "whami - PALcode for whami instruction" 4192//+ | |
| 4193// | 3215// |
| 3216// whami - PALcode for whami instruction 3217// |
|
| 4194// Entry: 4195// Vectored into via hardware PALcode instruction dispatch. 4196// 4197// Function: 4198// v0 (r0) <- whami | 3218// Entry: 3219// Vectored into via hardware PALcode instruction dispatch. 3220// 3221// Function: 3222// v0 (r0) <- whami |
| 4199//- | 3223// |
| 4200 CALL_PAL_PRIV(PAL_WHAMI_ENTRY) 4201Call_Pal_Whami: 4202 nop 4203 mfpr r0, pt_whami // Get Whami 4204 extbl r0, 1, r0 // Isolate just whami bits 4205 hw_rei 4206 | 3224 CALL_PAL_PRIV(PAL_WHAMI_ENTRY) 3225Call_Pal_Whami: 3226 nop 3227 mfpr r0, pt_whami // Get Whami 3228 extbl r0, 1, r0 // Isolate just whami bits 3229 hw_rei 3230 |
| 4207// .sbttl "retsys - PALcode for retsys instruction" | |
| 4208// | 3231// |
| 3232// retsys - PALcode for retsys instruction 3233// |
|
| 4209// Entry: 4210// Vectored into via hardware PALcode instruction dispatch. 4211// 00(sp) contains return pc 4212// 08(sp) contains r29 4213// 4214// Function: 4215// Return from system call. 4216// mode switched from kern to user. 4217// stacks swapped, ugp, upc restored. 4218// r23, r25 junked | 3234// Entry: 3235// Vectored into via hardware PALcode instruction dispatch. 3236// 00(sp) contains return pc 3237// 08(sp) contains r29 3238// 3239// Function: 3240// Return from system call. 3241// mode switched from kern to user. 3242// stacks swapped, ugp, upc restored. 3243// r23, r25 junked |
| 4219//- | 3244// |
| 4220 4221 CALL_PAL_PRIV(PAL_RETSYS_ENTRY) 4222Call_Pal_Retsys: 4223 lda r25, osfsf_c_size(sp) // pop stack 4224 bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr 4225 4226 mfpr r14, exc_addr // save exc_addr in case of fault 4227 ldq r23, osfsf_pc(sp) // get pc --- 17 unchanged lines hidden (view full) --- 4245// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal 4246 hw_rei_spe // and back 4247 4248 4249 CALL_PAL_PRIV(0x003E) 4250CallPal_OpcDec3E: 4251 br r31, osfpal_calpal_opcdec 4252 | 3245 3246 CALL_PAL_PRIV(PAL_RETSYS_ENTRY) 3247Call_Pal_Retsys: 3248 lda r25, osfsf_c_size(sp) // pop stack 3249 bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr 3250 3251 mfpr r14, exc_addr // save exc_addr in case of fault 3252 ldq r23, osfsf_pc(sp) // get pc --- 17 unchanged lines hidden (view full) --- 3270// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal 3271 hw_rei_spe // and back 3272 3273 3274 CALL_PAL_PRIV(0x003E) 3275CallPal_OpcDec3E: 3276 br r31, osfpal_calpal_opcdec 3277 |
| 4253// .sbttl "rti - PALcode for rti instruction" 4254//+ | |
| 4255// | 3278// |
| 3279// rti - PALcode for rti instruction 3280// |
|
| 4256// Entry: 4257// Vectored into via hardware PALcode instruction dispatch. 4258// 4259// Function: 4260// 00(sp) -> ps 4261// 08(sp) -> pc 4262// 16(sp) -> r29 (gp) 4263// 24(sp) -> r16 (a0) 4264// 32(sp) -> r17 (a1) 4265// 40(sp) -> r18 (a3) | 3281// Entry: 3282// Vectored into via hardware PALcode instruction dispatch. 3283// 3284// Function: 3285// 00(sp) -> ps 3286// 08(sp) -> pc 3287// 16(sp) -> r29 (gp) 3288// 24(sp) -> r16 (a0) 3289// 32(sp) -> r17 (a1) 3290// 40(sp) -> r18 (a3) |
| 4266//- | 3291// |
| 4267 4268 CALL_PAL_PRIV(PAL_RTI_ENTRY) | 3292 3293 CALL_PAL_PRIV(PAL_RTI_ENTRY) |
| 4269#ifdef SIMOS | |
| 4270 /* called once by platform_tlaser */ 4271 .globl Call_Pal_Rti | 3294 /* called once by platform_tlaser */ 3295 .globl Call_Pal_Rti |
| 4272#endif | |
| 4273Call_Pal_Rti: 4274 lda r25, osfsf_c_size(sp) // get updated sp 4275 bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr 4276 4277 mfpr r14, exc_addr // save PC in case of fault 4278 rc r31 // clear intr_flag 4279 4280 ldq r12, -6*8(r25) // get ps --- 10 unchanged lines hidden (view full) --- 4291 4292 and r12, osfps_m_mode, r11 // get mode 4293 mtpr r13, exc_addr // set return address 4294 4295 beq r11, rti_to_kern // br if rti to Kern 4296 br r31, rti_to_user // out of call_pal space 4297 4298 | 3296Call_Pal_Rti: 3297 lda r25, osfsf_c_size(sp) // get updated sp 3298 bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr 3299 3300 mfpr r14, exc_addr // save PC in case of fault 3301 rc r31 // clear intr_flag 3302 3303 ldq r12, -6*8(r25) // get ps --- 10 unchanged lines hidden (view full) --- 3314 3315 and r12, osfps_m_mode, r11 // get mode 3316 mtpr r13, exc_addr // set return address 3317 3318 beq r11, rti_to_kern // br if rti to Kern 3319 br r31, rti_to_user // out of call_pal space 3320 3321 |
| 4299// .sbttl "Start the Unprivileged CALL_PAL Entry Points" 4300// .sbttl "bpt- PALcode for bpt instruction" 4301//+ | 3322/////////////////////////////////////////////////// 3323// Start the Unprivileged CALL_PAL Entry Points 3324/////////////////////////////////////////////////// 3325 |
| 4302// | 3326// |
| 3327// bpt - PALcode for bpt instruction 3328// |
|
| 4303// Entry: 4304// Vectored into via hardware PALcode instruction dispatch. 4305// 4306// Function: 4307// Build stack frame 4308// a0 <- code 4309// a1 <- unpred 4310// a2 <- unpred 4311// vector via entIF 4312// | 3329// Entry: 3330// Vectored into via hardware PALcode instruction dispatch. 3331// 3332// Function: 3333// Build stack frame 3334// a0 <- code 3335// a1 <- unpred 3336// a2 <- unpred 3337// vector via entIF 3338// |
| 4313//- | |
| 4314// | 3339// |
| 3340// |
|
| 4315 .text 1 4316// . = 0x3000 4317 CALL_PAL_UNPRIV(PAL_BPT_ENTRY) 4318Call_Pal_Bpt: 4319 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 4320 mtpr r31, ev5__ps // Set Ibox current mode to kernel 4321 4322 bis r11, r31, r12 // Save PS for stack write --- 12 unchanged lines hidden (view full) --- 4335 4336 stq r16, osfsf_a0(sp) // save regs 4337 bis r31, osf_a0_bpt, r16 // set a0 4338 4339 stq r17, osfsf_a1(sp) // a1 4340 br r31, bpt_bchk_common // out of call_pal space 4341 4342 | 3341 .text 1 3342// . = 0x3000 3343 CALL_PAL_UNPRIV(PAL_BPT_ENTRY) 3344Call_Pal_Bpt: 3345 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 3346 mtpr r31, ev5__ps // Set Ibox current mode to kernel 3347 3348 bis r11, r31, r12 // Save PS for stack write --- 12 unchanged lines hidden (view full) --- 3361 3362 stq r16, osfsf_a0(sp) // save regs 3363 bis r31, osf_a0_bpt, r16 // set a0 3364 3365 stq r17, osfsf_a1(sp) // a1 3366 br r31, bpt_bchk_common // out of call_pal space 3367 3368 |
| 4343// .sbttl "bugchk- PALcode for bugchk instruction" 4344//+ | |
| 4345// | 3369// |
| 3370// bugchk - PALcode for bugchk instruction 3371// |
|
| 4346// Entry: 4347// Vectored into via hardware PALcode instruction dispatch. 4348// 4349// Function: 4350// Build stack frame 4351// a0 <- code 4352// a1 <- unpred 4353// a2 <- unpred 4354// vector via entIF 4355// | 3372// Entry: 3373// Vectored into via hardware PALcode instruction dispatch. 3374// 3375// Function: 3376// Build stack frame 3377// a0 <- code 3378// a1 <- unpred 3379// a2 <- unpred 3380// vector via entIF 3381// |
| 4356//- | |
| 4357// | 3382// |
| 3383// |
|
| 4358 CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY) 4359Call_Pal_Bugchk: 4360 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 4361 mtpr r31, ev5__ps // Set Ibox current mode to kernel 4362 4363 bis r11, r31, r12 // Save PS for stack write 4364 bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern 4365 --- 14 unchanged lines hidden (view full) --- 4380 stq r17, osfsf_a1(sp) // a1 4381 br r31, bpt_bchk_common // out of call_pal space 4382 4383 4384 CALL_PAL_UNPRIV(0x0082) 4385CallPal_OpcDec82: 4386 br r31, osfpal_calpal_opcdec 4387 | 3384 CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY) 3385Call_Pal_Bugchk: 3386 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 3387 mtpr r31, ev5__ps // Set Ibox current mode to kernel 3388 3389 bis r11, r31, r12 // Save PS for stack write 3390 bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern 3391 --- 14 unchanged lines hidden (view full) --- 3406 stq r17, osfsf_a1(sp) // a1 3407 br r31, bpt_bchk_common // out of call_pal space 3408 3409 3410 CALL_PAL_UNPRIV(0x0082) 3411CallPal_OpcDec82: 3412 br r31, osfpal_calpal_opcdec 3413 |
| 4388// .sbttl "callsys - PALcode for callsys instruction" 4389//+ | |
| 4390// | 3414// |
| 3415// callsys - PALcode for callsys instruction 3416// |
|
| 4391// Entry: 4392// Vectored into via hardware PALcode instruction dispatch. 4393// 4394// Function: 4395// Switch mode to kernel and build a callsys stack frame. 4396// sp = ksp 4397// gp = kgp 4398// t8 - t10 (r22-r24) trashed 4399// | 3417// Entry: 3418// Vectored into via hardware PALcode instruction dispatch. 3419// 3420// Function: 3421// Switch mode to kernel and build a callsys stack frame. 3422// sp = ksp 3423// gp = kgp 3424// t8 - t10 (r22-r24) trashed 3425// |
| 4400//- | |
| 4401// | 3426// |
| 3427// |
|
| 4402 CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY) 4403Call_Pal_Callsys: 4404 4405 and r11, osfps_m_mode, r24 // get mode 4406 mfpr r22, pt_ksp // get ksp 4407 4408 beq r24, sys_from_kern // sysCall from kern is not allowed 4409 mfpr r12, pt_entsys // get address of callSys routine 4410 | 3428 CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY) 3429Call_Pal_Callsys: 3430 3431 and r11, osfps_m_mode, r24 // get mode 3432 mfpr r22, pt_ksp // get ksp 3433 3434 beq r24, sys_from_kern // sysCall from kern is not allowed 3435 mfpr r12, pt_entsys // get address of callSys routine 3436 |
| 4411//+ | 3437// |
| 4412// from here on we know we are in user going to Kern | 3438// from here on we know we are in user going to Kern |
| 4413//- | 3439// |
| 4414 mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 4415 mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 4416 4417 bis r31, r31, r11 // PS=0 (mode=kern) 4418 mfpr r23, exc_addr // get pc 4419 4420 mtpr r30, pt_usp // save usp 4421 lda sp, 0-osfsf_c_size(r22)// set new sp --- 13 unchanged lines hidden (view full) --- 4435 CALL_PAL_UNPRIV(0x0084) 4436CallPal_OpcDec84: 4437 br r31, osfpal_calpal_opcdec 4438 4439 CALL_PAL_UNPRIV(0x0085) 4440CallPal_OpcDec85: 4441 br r31, osfpal_calpal_opcdec 4442 | 3440 mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 3441 mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 3442 3443 bis r31, r31, r11 // PS=0 (mode=kern) 3444 mfpr r23, exc_addr // get pc 3445 3446 mtpr r30, pt_usp // save usp 3447 lda sp, 0-osfsf_c_size(r22)// set new sp --- 13 unchanged lines hidden (view full) --- 3461 CALL_PAL_UNPRIV(0x0084) 3462CallPal_OpcDec84: 3463 br r31, osfpal_calpal_opcdec 3464 3465 CALL_PAL_UNPRIV(0x0085) 3466CallPal_OpcDec85: 3467 br r31, osfpal_calpal_opcdec 3468 |
| 4443// .sbttl "imb - PALcode for imb instruction" 4444//+ | |
| 4445// | 3469// |
| 3470// imb - PALcode for imb instruction 3471// |
|
| 4446// Entry: 4447// Vectored into via hardware PALcode instruction dispatch. 4448// 4449// Function: 4450// Flush the writebuffer and flush the Icache 4451// | 3472// Entry: 3473// Vectored into via hardware PALcode instruction dispatch. 3474// 3475// Function: 3476// Flush the writebuffer and flush the Icache 3477// |
| 4452//- | |
| 4453// | 3478// |
| 3479// |
|
| 4454 CALL_PAL_UNPRIV(PAL_IMB_ENTRY) 4455Call_Pal_Imb: 4456 mb // Clear the writebuffer 4457 mfpr r31, ev5__mcsr // Sync with clear 4458 nop 4459 nop 4460 br r31, pal_ic_flush // Flush Icache 4461 4462 | 3480 CALL_PAL_UNPRIV(PAL_IMB_ENTRY) 3481Call_Pal_Imb: 3482 mb // Clear the writebuffer 3483 mfpr r31, ev5__mcsr // Sync with clear 3484 nop 3485 nop 3486 br r31, pal_ic_flush // Flush Icache 3487 3488 |
| 4463// .sbttl "CALL_PAL OPCDECs" | 3489// CALL_PAL OPCDECs |
| 4464 4465 CALL_PAL_UNPRIV(0x0087) 4466CallPal_OpcDec87: 4467 br r31, osfpal_calpal_opcdec 4468 4469 CALL_PAL_UNPRIV(0x0088) 4470CallPal_OpcDec88: 4471 br r31, osfpal_calpal_opcdec --- 77 unchanged lines hidden (view full) --- 4549 CALL_PAL_UNPRIV(0x009C) 4550CallPal_OpcDec9C: 4551 br r31, osfpal_calpal_opcdec 4552 4553 CALL_PAL_UNPRIV(0x009D) 4554CallPal_OpcDec9D: 4555 br r31, osfpal_calpal_opcdec 4556 | 3490 3491 CALL_PAL_UNPRIV(0x0087) 3492CallPal_OpcDec87: 3493 br r31, osfpal_calpal_opcdec 3494 3495 CALL_PAL_UNPRIV(0x0088) 3496CallPal_OpcDec88: 3497 br r31, osfpal_calpal_opcdec --- 77 unchanged lines hidden (view full) --- 3575 CALL_PAL_UNPRIV(0x009C) 3576CallPal_OpcDec9C: 3577 br r31, osfpal_calpal_opcdec 3578 3579 CALL_PAL_UNPRIV(0x009D) 3580CallPal_OpcDec9D: 3581 br r31, osfpal_calpal_opcdec 3582 |
| 4557// .sbttl "rdunique - PALcode for rdunique instruction" 4558//+ | |
| 4559// | 3583// |
| 3584// rdunique - PALcode for rdunique instruction 3585// |
|
| 4560// Entry: 4561// Vectored into via hardware PALcode instruction dispatch. 4562// 4563// Function: 4564// v0 (r0) <- unique 4565// | 3586// Entry: 3587// Vectored into via hardware PALcode instruction dispatch. 3588// 3589// Function: 3590// v0 (r0) <- unique 3591// |
| 4566//- | |
| 4567// | 3592// |
| 3593// |
|
| 4568 CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY) 4569CALL_PALrdunique_: 4570 mfpr r0, pt_pcbb // get pcb pointer | 3594 CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY) 3595CALL_PALrdunique_: 3596 mfpr r0, pt_pcbb // get pcb pointer |
| 4571 ldqp r0, osfpcb_q_unique(r0) // get new value | 3597 ldq_p r0, osfpcb_q_unique(r0) // get new value |
| 4572 4573 hw_rei 4574 | 3598 3599 hw_rei 3600 |
| 4575// .sbttl "wrunique - PALcode for wrunique instruction" 4576//+ | |
| 4577// | 3601// |
| 3602// wrunique - PALcode for wrunique instruction 3603// |
|
| 4578// Entry: 4579// Vectored into via hardware PALcode instruction dispatch. 4580// 4581// Function: 4582// unique <- a0 (r16) 4583// | 3604// Entry: 3605// Vectored into via hardware PALcode instruction dispatch. 3606// 3607// Function: 3608// unique <- a0 (r16) 3609// |
| 4584//- | |
| 4585// | 3610// |
| 3611// |
|
| 4586CALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY) 4587CALL_PAL_Wrunique: 4588 nop 4589 mfpr r12, pt_pcbb // get pcb pointer | 3612CALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY) 3613CALL_PAL_Wrunique: 3614 nop 3615 mfpr r12, pt_pcbb // get pcb pointer |
| 4590 stqp r16, osfpcb_q_unique(r12)// get new value | 3616 stq_p r16, osfpcb_q_unique(r12)// get new value |
| 4591 nop // Pad palshadow write 4592 hw_rei // back 4593 | 3617 nop // Pad palshadow write 3618 hw_rei // back 3619 |
| 4594// .sbttl "CALL_PAL OPCDECs" | 3620// CALL_PAL OPCDECs |
| 4595 4596 CALL_PAL_UNPRIV(0x00A0) 4597CallPal_OpcDecA0: 4598 br r31, osfpal_calpal_opcdec 4599 4600 CALL_PAL_UNPRIV(0x00A1) 4601CallPal_OpcDecA1: 4602 br r31, osfpal_calpal_opcdec --- 26 unchanged lines hidden (view full) --- 4629CallPal_OpcDecA8: 4630 br r31, osfpal_calpal_opcdec 4631 4632 CALL_PAL_UNPRIV(0x00A9) 4633CallPal_OpcDecA9: 4634 br r31, osfpal_calpal_opcdec 4635 4636 | 3621 3622 CALL_PAL_UNPRIV(0x00A0) 3623CallPal_OpcDecA0: 3624 br r31, osfpal_calpal_opcdec 3625 3626 CALL_PAL_UNPRIV(0x00A1) 3627CallPal_OpcDecA1: 3628 br r31, osfpal_calpal_opcdec --- 26 unchanged lines hidden (view full) --- 3655CallPal_OpcDecA8: 3656 br r31, osfpal_calpal_opcdec 3657 3658 CALL_PAL_UNPRIV(0x00A9) 3659CallPal_OpcDecA9: 3660 br r31, osfpal_calpal_opcdec 3661 3662 |
| 4637// .sbttl "gentrap - PALcode for gentrap instruction" 4638//+ | 3663// 3664// gentrap - PALcode for gentrap instruction 3665// |
| 4639// CALL_PAL_gentrap: 4640// Entry: 4641// Vectored into via hardware PALcode instruction dispatch. 4642// 4643// Function: 4644// Build stack frame 4645// a0 <- code 4646// a1 <- unpred 4647// a2 <- unpred 4648// vector via entIF 4649// | 3666// CALL_PAL_gentrap: 3667// Entry: 3668// Vectored into via hardware PALcode instruction dispatch. 3669// 3670// Function: 3671// Build stack frame 3672// a0 <- code 3673// a1 <- unpred 3674// a2 <- unpred 3675// vector via entIF 3676// |
| 4650//- | 3677// |
| 4651 4652 CALL_PAL_UNPRIV(0x00AA) 4653// unsupported in Hudson code .. pboyle Nov/95 4654CALL_PAL_gentrap: 4655 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 4656 mtpr r31, ev5__ps // Set Ibox current mode to kernel 4657 4658 bis r11, r31, r12 // Save PS for stack write --- 12 unchanged lines hidden (view full) --- 4671 4672 stq r16, osfsf_a0(sp) // save regs 4673 bis r31, osf_a0_gentrap, r16// set a0 4674 4675 stq r17, osfsf_a1(sp) // a1 4676 br r31, bpt_bchk_common // out of call_pal space 4677 4678 | 3678 3679 CALL_PAL_UNPRIV(0x00AA) 3680// unsupported in Hudson code .. pboyle Nov/95 3681CALL_PAL_gentrap: 3682 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 3683 mtpr r31, ev5__ps // Set Ibox current mode to kernel 3684 3685 bis r11, r31, r12 // Save PS for stack write --- 12 unchanged lines hidden (view full) --- 3698 3699 stq r16, osfsf_a0(sp) // save regs 3700 bis r31, osf_a0_gentrap, r16// set a0 3701 3702 stq r17, osfsf_a1(sp) // a1 3703 br r31, bpt_bchk_common // out of call_pal space 3704 3705 |
| 4679// .sbttl "CALL_PAL OPCDECs" | 3706// CALL_PAL OPCDECs |
| 4680 4681 CALL_PAL_UNPRIV(0x00AB) 4682CallPal_OpcDecAB: 4683 br r31, osfpal_calpal_opcdec 4684 4685 CALL_PAL_UNPRIV(0x00AC) 4686CallPal_OpcDecAC: 4687 br r31, osfpal_calpal_opcdec --- 80 unchanged lines hidden (view full) --- 4768/* OSF/1 CALL_PAL CONTINUATION AREA */ 4769/*======================================================================*/ 4770 4771 .text 2 4772 4773 . = 0x4000 4774 4775 | 3707 3708 CALL_PAL_UNPRIV(0x00AB) 3709CallPal_OpcDecAB: 3710 br r31, osfpal_calpal_opcdec 3711 3712 CALL_PAL_UNPRIV(0x00AC) 3713CallPal_OpcDecAC: 3714 br r31, osfpal_calpal_opcdec --- 80 unchanged lines hidden (view full) --- 3795/* OSF/1 CALL_PAL CONTINUATION AREA */ 3796/*======================================================================*/ 3797 3798 .text 2 3799 3800 . = 0x4000 3801 3802 |
| 4776// .sbttl "Continuation of MTPR_PERFMON" | 3803// Continuation of MTPR_PERFMON |
| 4777 ALIGN_BLOCK | 3804 ALIGN_BLOCK |
| 4778#if perfmon_debug == 0 | |
| 4779 // "real" performance monitoring code 4780// mux ctl 4781perfmon_muxctl: 4782 lda r8, 1(r31) // get a 1 4783 sll r8, pmctr_v_sel0, r8 // move to sel0 position 4784 or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask 4785 and r17, r8, r25 // isolate pmctr mux select bits 4786 mfpr r0, ev5__pmctr --- 12 unchanged lines hidden (view full) --- 4799 4800 lda r8, 0x3F(r31) // build mux select mask 4801 sll r8, bc_ctl_v_pm_mux_sel, r8 4802 4803 and r17, r8, r25 // isolate bc_ctl mux select bits 4804 bic r16, r8, r16 // isolate old mux select bits 4805 or r16, r25, r25 // create new bc_ctl 4806 mb // clear out cbox for future ipr write | 3805 // "real" performance monitoring code 3806// mux ctl 3807perfmon_muxctl: 3808 lda r8, 1(r31) // get a 1 3809 sll r8, pmctr_v_sel0, r8 // move to sel0 position 3810 or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask 3811 and r17, r8, r25 // isolate pmctr mux select bits 3812 mfpr r0, ev5__pmctr --- 12 unchanged lines hidden (view full) --- 3825 3826 lda r8, 0x3F(r31) // build mux select mask 3827 sll r8, bc_ctl_v_pm_mux_sel, r8 3828 3829 and r17, r8, r25 // isolate bc_ctl mux select bits 3830 bic r16, r8, r16 // isolate old mux select bits 3831 or r16, r25, r25 // create new bc_ctl 3832 mb // clear out cbox for future ipr write |
| 4807 stqp r25, ev5__bc_ctl(r14) // store to cbox ipr | 3833 stq_p r25, ev5__bc_ctl(r14) // store to cbox ipr |
| 4808 mb // clear out cbox for future ipr write 4809 4810//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr 4811// adapted from ev5_pal_macros.mar 4812 mfpr r16, pt_impure 4813 lda r16, CNS_Q_IPR(r16) 4814 SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16); 4815 --- 54 unchanged lines hidden (view full) --- 4870 4871perfmon_en_cont: 4872 mfpr r8, pt_pcbb // get PCB base 4873//orig get_pmctr_ctl r25, r25 4874 mfpr r25, pt_impure 4875 lda r25, CNS_Q_IPR(r25) 4876 RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25); 4877 | 3834 mb // clear out cbox for future ipr write 3835 3836//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr 3837// adapted from ev5_pal_macros.mar 3838 mfpr r16, pt_impure 3839 lda r16, CNS_Q_IPR(r16) 3840 SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16); 3841 --- 54 unchanged lines hidden (view full) --- 3896 3897perfmon_en_cont: 3898 mfpr r8, pt_pcbb // get PCB base 3899//orig get_pmctr_ctl r25, r25 3900 mfpr r25, pt_impure 3901 lda r25, CNS_Q_IPR(r25) 3902 RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25); 3903 |
| 4878 ldqp r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword | 3904 ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword |
| 4879 mfpr r14, ev5__pmctr // read ibox pmctr ipr 4880 srl r16, osfpcb_v_pme, r16 // get pme bit 4881 mfpr r13, icsr 4882 and r16, 1, r16 // isolate pme bit 4883 4884 // this code only needed in pass2 and later | 3905 mfpr r14, ev5__pmctr // read ibox pmctr ipr 3906 srl r16, osfpcb_v_pme, r16 // get pme bit 3907 mfpr r13, icsr 3908 and r16, 1, r16 // isolate pme bit 3909 3910 // this code only needed in pass2 and later |
| 4885//orig sget_addr r12, 1<<icsr_v_pmp, r31 | |
| 4886 lda r12, 1<<icsr_v_pmp(r31) // pb 4887 bic r13, r12, r13 // clear pmp bit 4888 sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position 4889 or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear | 3911 lda r12, 1<<icsr_v_pmp(r31) // pb 3912 bic r13, r12, r13 // clear pmp bit 3913 sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position 3914 or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear |
| 4890 ev5_pass2 mtpr r13, icsr // update icsr | 3915 mtpr r13, icsr // update icsr |
| 4891 | 3916 |
| 4892#if ev5_p1 != 0 4893 lda r12, 1(r31) 4894 cmovlbc r25, r12, r16 // r16<0> set if either pme=1 or sprocess=0 (sprocess in bit 0 of r25) 4895#else | |
| 4896 bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable) | 3917 bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable) |
| 4897#endif | |
| 4898 4899 sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions 4900 bis r14, r31, r13 // copy pmctr 4901 4902perfmon_en_ctr0: // and begin with ctr0 4903 blbc r17, perfmon_en_ctr1 // do not enable ctr0 4904 4905 blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field --- 71 unchanged lines hidden (view full) --- 4977perfmon_ctl: 4978 4979// set mode 4980//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 4981 mfpr r12, pt_impure 4982 lda r12, CNS_Q_IPR(r12) 4983 RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 4984 | 3918 3919 sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions 3920 bis r14, r31, r13 // copy pmctr 3921 3922perfmon_en_ctr0: // and begin with ctr0 3923 blbc r17, perfmon_en_ctr1 // do not enable ctr0 3924 3925 blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field --- 71 unchanged lines hidden (view full) --- 3997perfmon_ctl: 3998 3999// set mode 4000//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 4001 mfpr r12, pt_impure 4002 lda r12, CNS_Q_IPR(r12) 4003 RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 4004 |
| 4985//orig get_addr r8, (1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk), r31 // build mode mask for pmctr register | 4005 // build mode mask for pmctr register |
| 4986 LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk))) 4987 mfpr r0, ev5__pmctr 4988 and r17, r8, r25 // isolate pmctr mode bits 4989 bic r0, r8, r0 // clear old mode bits 4990 or r0, r25, r25 // or in new mode bits 4991 mtpr r25, ev5__pmctr 4992 | 4006 LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk))) 4007 mfpr r0, ev5__pmctr 4008 and r17, r8, r25 // isolate pmctr mode bits 4009 bic r0, r8, r0 // clear old mode bits 4010 or r0, r25, r25 // or in new mode bits 4011 mtpr r25, ev5__pmctr 4012 |
| 4993//;the following code will only be used in pass2, but should not hurt anything if run in pass1. | 4013 // the following code will only be used in pass2, but should 4014 // not hurt anything if run in pass1. |
| 4994 mfpr r8, icsr 4995 lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0 4996 bic r8, r25, r8 // clear old pma bit 4997 cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1 4998 or r8, r25, r8 | 4015 mfpr r8, icsr 4016 lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0 4017 bic r8, r25, r8 // clear old pma bit 4018 cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1 4019 or r8, r25, r8 |
| 4999 ev5_pass2 mtpr r8, icsr // 4 bubbles to hw_rei | 4020 mtpr r8, icsr // 4 bubbles to hw_rei |
| 5000 mfpr r31, pt0 // pad icsr write 5001 mfpr r31, pt0 // pad icsr write 5002 | 4021 mfpr r31, pt0 // pad icsr write 4022 mfpr r31, pt0 // pad icsr write 4023 |
| 5003//;the following code not needed for pass2 and later, but should work anyway. | 4024 // the following code not needed for pass2 and later, but 4025 // should work anyway. |
| 5004 bis r14, 1, r14 // set for select processes 5005 blbs r17, perfmon_sp // branch if select processes 5006 bic r14, 1, r14 // all processes 5007perfmon_sp: 5008//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register 5009 SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 5010 br r31, perfmon_success 5011 5012// counter frequency select 5013perfmon_freq: 5014//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 5015 mfpr r12, pt_impure 5016 lda r12, CNS_Q_IPR(r12) 5017 RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 5018 5019 lda r8, 0x3F(r31) 5020//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field | 4026 bis r14, 1, r14 // set for select processes 4027 blbs r17, perfmon_sp // branch if select processes 4028 bic r14, 1, r14 // all processes 4029perfmon_sp: 4030//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register 4031 SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 4032 br r31, perfmon_success 4033 4034// counter frequency select 4035perfmon_freq: 4036//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 4037 mfpr r12, pt_impure 4038 lda r12, CNS_Q_IPR(r12) 4039 RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 4040 4041 lda r8, 0x3F(r31) 4042//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field |
| 5021// I guess this should be a shift of 4 bits from the above control register structure .. pb | 4043// I guess this should be a shift of 4 bits from the above control register structure |
| 5022#define pmctr_ctl_v_frq2_SHIFT 4 5023 sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field 5024 5025 and r8, r17, r17 5026 bic r14, r8, r14 // clear out old frequency select bits 5027 5028 or r17, r14, r14 // or in new frequency select info 5029//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register --- 8 unchanged lines hidden (view full) --- 5038 hw_rei // back to user 5039 5040// write counters 5041perfmon_wr: 5042 mfpr r14, ev5__pmctr 5043 lda r8, 0x3FFF(r31) // ctr2<13:0> mask 5044 sll r8, pmctr_v_ctr2, r8 5045 | 4044#define pmctr_ctl_v_frq2_SHIFT 4 4045 sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field 4046 4047 and r8, r17, r17 4048 bic r14, r8, r14 // clear out old frequency select bits 4049 4050 or r17, r14, r14 // or in new frequency select info 4051//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register --- 8 unchanged lines hidden (view full) --- 4060 hw_rei // back to user 4061 4062// write counters 4063perfmon_wr: 4064 mfpr r14, ev5__pmctr 4065 lda r8, 0x3FFF(r31) // ctr2<13:0> mask 4066 sll r8, pmctr_v_ctr2, r8 4067 |
| 5046//orig get_addr r9, 0xFFFFFFFF, r31, verify=0 // ctr2<15:0>,ctr1<15:0> mask 5047 LDLI(r9, (0xFFFFFFFF)) | 4068 LDLI(r9, (0xFFFFFFFF)) // ctr2<15:0>,ctr1<15:0> mask |
| 5048 sll r9, pmctr_v_ctr1, r9 5049 or r8, r9, r8 // or ctr2, ctr1, ctr0 mask 5050 bic r14, r8, r14 // clear ctr fields 5051 and r17, r8, r25 // clear all but ctr fields 5052 or r25, r14, r14 // write ctr fields 5053 mtpr r14, ev5__pmctr // update pmctr ipr 5054 5055 mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy) 5056 5057perfmon_success: 5058 or r31, 1, r0 // set success 5059 hw_rei // back to user 5060 5061perfmon_unknown: 5062 or r31, r31, r0 // set fail 5063 hw_rei // back to user 5064 | 4069 sll r9, pmctr_v_ctr1, r9 4070 or r8, r9, r8 // or ctr2, ctr1, ctr0 mask 4071 bic r14, r8, r14 // clear ctr fields 4072 and r17, r8, r25 // clear all but ctr fields 4073 or r25, r14, r14 // write ctr fields 4074 mtpr r14, ev5__pmctr // update pmctr ipr 4075 4076 mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy) 4077 4078perfmon_success: 4079 or r31, 1, r0 // set success 4080 hw_rei // back to user 4081 4082perfmon_unknown: 4083 or r31, r31, r0 // set fail 4084 hw_rei // back to user 4085 |
| 5065#else | |
| 5066 | 4086 |
| 5067// end of "real code", start of debug code | 4087////////////////////////////////////////////////////////// 4088// Copy code 4089////////////////////////////////////////////////////////// |
| 5068 | 4090 |
| 5069//+ 5070// Debug environment: 5071// (in pass2, always set icsr<pma> to ensure master counter enable is on) 5072// R16 = 0 Write to on-chip performance monitor ipr 5073// r17 = on-chip ipr 5074// r0 = return value of read of on-chip performance monitor ipr 5075// R16 = 1 Setup Cbox mux selects 5076// r17 = Cbox mux selects in same position as in bc_ctl ipr. 5077// r0 = return value of read of on-chip performance monitor ipr 5078// 5079//- 5080pal_perfmon_debug: 5081 mfpr r8, icsr 5082 lda r9, 1<<icsr_v_pma(r31) 5083 bis r8, r9, r8 5084 mtpr r8, icsr 5085 5086 mfpr r0, ev5__pmctr // read old value 5087 bne r16, cbox_mux_sel 5088 5089 mtpr r17, ev5__pmctr // update pmctr ipr 5090 br r31, end_pm 5091 5092cbox_mux_sel: 5093 // ok, now tackle cbox mux selects 5094 ldah r14, 0xfff0(r31) 5095 zap r14, 0xE0, r14 // Get Cbox IPR base 5096//orig get_bc_ctl_shadow r16 // bc_ctl returned 5097 mfpr r16, pt_impure 5098 lda r16, CNS_Q_IPR(r16) 5099 RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16); 5100 5101 lda r8, 0x3F(r31) // build mux select mask 5102 sll r8, BC_CTL_V_PM_MUX_SEL, r8 5103 5104 and r17, r8, r25 // isolate bc_ctl mux select bits 5105 bic r16, r8, r16 // isolate old mux select bits 5106 or r16, r25, r25 // create new bc_ctl 5107 mb // clear out cbox for future ipr write 5108 stqp r25, ev5__bc_ctl(r14) // store to cbox ipr 5109 mb // clear out cbox for future ipr write 5110//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr 5111 mfpr r16, pt_impure 5112 lda r16, CNS_Q_IPR(r16) 5113 SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16); 5114 5115end_pm: hw_rei 5116 5117#endif 5118 5119 5120//;The following code is a workaround for a cpu bug where Istream prefetches to 5121//;super-page address space in user mode may escape off-chip. 5122#if spe_fix != 0 5123 5124 ALIGN_BLOCK 5125hw_rei_update_spe: 5126 mfpr r12, pt_misc // get previous mode 5127 srl r11, osfps_v_mode, r10 // isolate current mode bit 5128 and r10, 1, r10 5129 extbl r12, 7, r8 // get previous mode field 5130 and r8, 1, r8 // isolate previous mode bit 5131 cmpeq r10, r8, r8 // compare previous and current modes 5132 beq r8, hw_rei_update_spe_5_ 5133 hw_rei // if same, just return 5134 5135hw_rei_update_spe_5_: 5136 5137#if fill_err_hack != 0 5138 5139 fill_error_hack 5140#endif 5141 5142 mfpr r8, icsr // get current icsr value 5143 ldah r9, (2<<(icsr_v_spe-16))(r31) // get spe bit mask 5144 bic r8, r9, r8 // disable spe 5145 xor r10, 1, r9 // flip mode for new spe bit 5146 sll r9, icsr_v_spe+1, r9 // shift into position 5147 bis r8, r9, r8 // enable/disable spe 5148 lda r9, 1(r31) // now update our flag 5149 sll r9, pt_misc_v_cm, r9 // previous mode saved bit mask 5150 bic r12, r9, r12 // clear saved previous mode 5151 sll r10, pt_misc_v_cm, r9 // current mode saved bit mask 5152 bis r12, r9, r12 // set saved current mode 5153 mtpr r12, pt_misc // update pt_misc 5154 mtpr r8, icsr // update icsr 5155 5156#if osf_chm_fix != 0 5157 5158 5159 blbc r10, hw_rei_update_spe_10_ // branch if not user mode 5160 5161 mb // ensure no outstanding fills 5162 lda r12, 1<<dc_mode_v_dc_ena(r31) // User mode 5163 mtpr r12, dc_mode // Turn on dcache 5164 mtpr r31, dc_flush // and flush it 5165 br r31, pal_ic_flush 5166 5167hw_rei_update_spe_10_: mfpr r9, pt_pcbb // Kernel mode 5168 ldqp r9, osfpcb_q_Fen(r9) // get FEN 5169 blbc r9, pal_ic_flush // return if FP disabled 5170 mb // ensure no outstanding fills 5171 mtpr r31, dc_mode // turn off dcache 5172#endif 5173 5174 5175 br r31, pal_ic_flush // Pal restriction - must flush Icache if changing ICSR<SPE> 5176#endif 5177 5178 | |
| 5179copypal_impl: 5180 mov r16, r0 | 4091copypal_impl: 4092 mov r16, r0 |
| 5181 ble r18, finished #if len <=0 we are finished | 4093#ifdef CACHE_COPY 4094#ifndef CACHE_COPY_UNALIGNED 4095 and r16, 63, r8 4096 and r17, 63, r9 4097 bis r8, r9, r8 4098 bne r8, cache_copy_done 4099#endif 4100 bic r18, 63, r8 4101 and r18, 63, r18 4102 beq r8, cache_copy_done 4103cache_loop: 4104 ldf f17, 0(r16) 4105 stf f17, 0(r16) 4106 addq r17, 64, r17 4107 addq r16, 64, r16 4108 subq r8, 64, r8 4109 bne r8, cache_loop 4110cache_copy_done: 4111#endif 4112 ble r18, finished // if len <=0 we are finished |
| 5182 ldq_u r8, 0(r17) 5183 xor r17, r16, r9 5184 and r9, 7, r9 5185 and r16, 7, r10 5186 bne r9, unaligned 5187 beq r10, aligned 5188 ldq_u r9, 0(r16) 5189 addq r18, r10, r18 --- 106 unchanged lines hidden --- | 4113 ldq_u r8, 0(r17) 4114 xor r17, r16, r9 4115 and r9, 7, r9 4116 and r16, 7, r10 4117 bne r9, unaligned 4118 beq r10, aligned 4119 ldq_u r9, 0(r16) 4120 addq r18, r10, r18 --- 106 unchanged lines hidden --- |