33c33,55
< Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development Company, L.P.
---
> * Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development
> * Company, L.P.
> *
> * Permission is hereby granted, free of charge, to any person
> * obtaining a copy of this software and associated documentation
> * files (the "Software"), to deal in the Software without
> * restriction, including without limitation the rights to use, copy,
> * modify, merge, publish, distribute, sublicense, and/or sell copies
> * of the Software, and to permit persons to whom the Software is
> * furnished to do so, subject to the following conditions:
> *
> * The above copyright notice and this permission notice shall be
> * included in all copies or substantial portions of the Software.
> *
> * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> * SOFTWARE.
> */
35,53d56
< Permission is hereby granted, free of charge, to any person obtaining a copy of
< this software and associated documentation files (the "Software"), to deal in
< the Software without restriction, including without limitation the rights to
< use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
< of the Software, and to permit persons to whom the Software is furnished to do
< so, subject to the following conditions:
<
< The above copyright notice and this permission notice shall be included in all
< copies or substantial portions of the Software.
<
< THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
< IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
< FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
< AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
< LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
< OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
< SOFTWARE.
< */
<
56,61d58
<
< // build_fixed_image: not sure what means
< // real_mm to be replaced during rewrite
< // remove_save_state remove_restore_state can be remooved to save space ??
<
<
71d67
< #ifdef SIMOS
73,77d68
< #else
< #define DEBUGSTORE(c) \
< lda r13, c(zero) ; \
< bsr r25, debugstore
< #endif
84,112c75,76
< #define egore 0
< #define acore 0
< #define beh_model 0
< #define ev5_p2 1
< #define ev5_p1 0
< #define ldvpte_bug_fix 1
< #define osf_chm_fix 0
<
< // Do we want to do this?? pb
< #define spe_fix 0
< // Do we want to do this?? pb
< #define build_fixed_image 0
<
< #define ev5_pass2
< #define enable_p4_fixups 0
< #define osf_svmin 1
< #define enable_physical_console 0
< #define fill_err_hack 0
< #define icflush_on_tbix 0
< #define max_cpuid 1
< #define perfmon_debug 0
< #define rawhide_system 0
< #define rax_mode 0
<
<
< // This is the fix for the user-mode super page references causing the machine to crash.
< #if (spe_fix == 1) && (build_fixed_image==1)
< #define hw_rei_spe br r31, hw_rei_update_spe
< #else
---
> // This is the fix for the user-mode super page references causing the
> // machine to crash.
114d77
< #endif
116,315d78
<
< // redefine a few of the distribution-code names to match the Hudson gas names.
< // opcodes
< #define ldqp ldq_p
< #define stqp stq_p
< #define ldlp ldl_p
< #define stlp stl_p
<
< #define r0 $0
< #define r1 $1
< #define r2 $2
< #define r3 $3
< #define r4 $4
< #define r5 $5
< #define r6 $6
< #define r7 $7
< #define r8 $8
< #define r9 $9
< #define r10 $10
< #define r11 $11
< #define r12 $12
< #define r13 $13
< #define r14 $14
< #define r15 $15
< #define r16 $16
< #define r17 $17
< #define r18 $18
< #define r19 $19
< #define r20 $20
< #define r21 $21
< #define r22 $22
< #define r23 $23
< #define r24 $24
< #define r25 $25
< #define r26 $26
< #define r27 $27
< #define r28 $28
< #define r29 $29
< #define r30 $30
< #define r31 $31
<
< // .title "EV5 OSF PAL"
< // .ident "V1.18"
< //
< //****************************************************************************
< //* *
< //* Copyright (c) 1992, 1993, 1994, 1995 *
< //* by DIGITAL Equipment Corporation, Maynard, Mass. *
< //* *
< //* This software is furnished under a license and may be used and copied *
< //* only in accordance with the terms of such license and with the *
< //* inclusion of the above copyright notice. This software or any other *
< //* copies thereof may not be provided or otherwise made available to any *
< //* other person. No title to and ownership of the software is hereby *
< //* transferred. *
< //* *
< //* The information in this software is subject to change without notice *
< //* and should not be construed as a commitment by DIGITAL Equipment *
< //* Corporation. *
< //* *
< //* DIGITAL assumes no responsibility for the use or reliability of its *
< //* software on equipment which is not supplied by DIGITAL. *
< //* *
< //****************************************************************************
<
< // .sbttl "Edit History"
< //+
< // Who Rev When What
< // ------------ --- ----------- --------------------------------
< // DB 0.0 03-Nov-1992 Start
< // DB 0.1 28-Dec-1992 add swpctx
< // DB 0.2 05-Jan-1993 Bug: PVC found mtpr dtb_CM -> virt ref bug
< // DB 0.3 11-Jan-1993 rearrange trap entry points
< // DB 0.4 01-Feb-1993 add tbi
< // DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal
< // DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14)
< // DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC
< // Bug: typo on register number for store in wrunique
< // Bug: rti to kern uses r16 as scratch
< // Bug: callsys saving wrong value in pt_usp
< // DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp
< // DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice
< // Bug: rti stl_c could corrupt the stack
< // Bug: unaligned returning wrong value in r17 (or should be and)
< // DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt
< // DB 0.11 23-Feb-1993 Turn caches on in reset flow
< // DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow
< // DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses
< // DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS
< // DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES
< // DB 0.16 12-May-1993 Update reset
< // New restriction: no mfpr exc_addr in cycle 1 of call_pal flows
< // Bug: in wrmces, not clearing DPC, DSC
< // Update swppal
< // Add pal bugchecks, pal_save_state, pal_restore_state
< // DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps.
< // New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn
< // DB 0.18 26-May-1993 PVC fixes
< // JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores
< // JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl
< // Bug: exc_addr was being loaded before stores that could dtb_miss in the following
< // routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN
< // JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines:
< // TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN::
< // dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler:
< // osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN::
< // Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles
< // JM 0.22 28-jul-1993 Add WRIPIR instruction
< // JM 0.23 05-aug-1993 Bump version number for release
< // JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation
< // JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals;
< // New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode),
< // and SWPCTX
< // JM 0.26 07-oct-1993 Re-implement pal_version
< // JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM
< // JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush
< // JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead
< // of mm_stat<opcode>. mm_stat contains original opcode, not hw_ld.
< // JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys
< // JM 0.31 15-nov-1993 BUG: WRFEN trashing r0
< // JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0
< // JM 0.33 24-nov-1993 save/restore_state -
< // BUG: use ivptbr to restore mvptbr
< // BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit
< // CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors
< // JM 0.34 20-dec-1993 BUG: set r11<mode> to kernel for ksnv halt case
< // BUG: generate ksnv halt when tb miss on kernel stack accesses
< // save exc_addr in r14 for invalid_dpte stack builder
< // JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in
< // the same shadow
< // JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS
< // New palcode restiction: mt icsr<fpe,hwe> --> 3 bubbles to hw_rei --affects wrfen
< // JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions
< // Hide impure area manipulations in macros
< // BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st
< // Add some pvc_violate statements
< // JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality;
< // Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments
< // Add code to ensure fen bit set in icsr before ldt
< // conditionally compile rax_more_reset out.
< // move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here
< // move rax reset stuff to ev5_osf_system_pal.m64
< // JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow
< // and performance monitoring bits
< // Change to save_state routine to save more iprs.
< // JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in
< // JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems)
< // remove_save_state,remove_restore_state;fix new pvc violation in save_state
< // JM 0.42 22-feb-1994 BUG: save_state overwriting r3
< // JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr
< // JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions
< // JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem)
< // New pal restriction in pal_restore_state: icsr<fpe>->floating instr = 3 bubbles
< // Add exc_sum and exc_mask to pal_save_state (not restore)
< // JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure
< // area.
< // Add performance counter support to swpctx and wrperfmon
< // JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix)
< // JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts
< // JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is
< // taken in the interrupt flow, stack is pushed twice.
< // SWPPAL - update to support ECO 59 to allow 0 as a valid address
< // Add itb flush to save/restore state routines
< // Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but
< // conforms to itbia restriction.
< // Added enable_physical_console flag (for enter/exit console routines only)
< // JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a
< // load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and
< // nmiss_fetch_err to nmiss_fetch_ldr31_err.
< // JM 1.00 1-aug-1994 Add pass2 support (swpctx)
< // JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2
< // JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2)
< // Moved perfmon code here from system file.
< // BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1)
< // JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit.
< // JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change
< // after ISR read, but we won't catch the ISR update. reverse order
< // JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31
< // JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code)
< // JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to
< // DTBMISS_SINGLE if not in palmode.
< // JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame
< // JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox
< // superpage mode in User mode and re-enable in kernel mode.
< // EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this.
< // JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2
< // ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid
< // cpu bug.
< // JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state
< // ES 1.13 17-mar-1995 Refine osf_chm_fix
< // ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix
< // ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state
< // Force pvc checking of exit_console
< // ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0
< // ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting)
< // instead of xor to maintain previous mode in pt_misc
< // ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does
< // not have pme set. The bits in icsr maintain the master enable state.
< // In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable
< //
322d84
< //-
324d85
< // .sbttl "PALtemp register usage"
326c87,90
< //+
---
> ///////////////////////////
> // PALtemp register usage
> ///////////////////////////
>
346c110,111
< // pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces
---
> // pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami,
> // pt_mces
355c120
< //-
---
> //
357c122,126
< // .sbttl "PALshadow register usage"
---
>
> /////////////////////////////
> // PALshadow register usage
> /////////////////////////////
>
359,360d127
< //+
< //
373,374d139
< //
< //-
376,387d140
< // .sbttl "ALPHA symbol definitions"
< // _OSF_PSDEF GLOBAL
< // _OSF_PTEDEF GLOBAL
< // _OSF_VADEF GLOBAL
< // _OSF_PCBDEF GLOBAL
< // _OSF_SFDEF GLOBAL
< // _OSF_MMCSR_DEF GLOBAL
< // _SCBDEF GLOBAL
< // _FRMDEF GLOBAL
< // _EXSDEF GLOBAL
< // _OSF_A0_DEF GLOBAL
< // _MCESDEF GLOBAL
389d141
< // .sbttl "EV5 symbol definitions"
391,405d142
< // _EV5DEF
< // _PALTEMP
< // _MM_STAT_DEF
< // _EV5_MM
< // _EV5_IPLDEF
<
< // _HALT_CODES GLOBAL
< // _MCHK_CODES GLOBAL
<
< // _PAL_IMPURE
< // _PAL_LOGOUT
<
<
<
<
413,614d149
<
< #define osfpal 1 // This is the PALcode for OSF.
<
< #ifndef rawhide_system
<
< #define rawhide_system 0
< #endif
<
<
< #ifndef real_mm
< // Page table translation vs 1-1 mapping
< #define real_mm 1
< #endif
<
<
< #ifndef rax_mode
<
< #define rax_mode 0
< #endif
<
< #ifndef egore
< // End of reset flow starts a program at 200000(hex).
< #define egore 1
< #endif
<
< #ifndef acore
< // End of reset flow starts a program at 40000(hex).
< #define acore 0
< #endif
<
<
< // assume acore+egore+rax_mode lt 2 // Assertion checker
<
< #ifndef beh_model
< // EV5 behavioral model specific code
< #define beh_model 1
< #endif
<
< #ifndef init_cbox
< // Reset flow init of Bcache and Scache
< #define init_cbox 1
< #endif
<
< #ifndef disable_crd
< // Decides whether the reset flow will disable
< #define disable_crd 0
< #endif
<
< // correctable read interrupts via ICSR
< #ifndef perfmon_debug
< #define perfmon_debug 0
< #endif
<
< #ifndef icflush_on_tbix
< #define icflush_on_tbix 0
< #endif
<
< #ifndef remove_restore_state
< #define remove_restore_state 0
< #endif
<
< #ifndef remove_save_state
< #define remove_save_state 0
< #endif
<
< #ifndef enable_physical_console
< #define enable_physical_console 0
< #endif
<
< #ifndef ev5_p1
< #define ev5_p1 0
< #endif
<
< #ifndef ev5_p2
< #define ev5_p2 1
< #endif
<
< // assume ev5_p1+ev5_p2 eq 1
<
< #ifndef ldvpte_bug_fix
< #define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow.
< #endif
<
< #ifndef spe_fix
< // If set, disable super-page mode in user mode and re-enable
< #define spe_fix 0
< #endif
< // in kernel. Workaround for cpu bug.
< #ifndef build_fixed_image
< #define build_fixed_image 0
< #endif
<
<
< #ifndef fill_err_hack
< // If set, disable fill_error mode in user mode and re-enable
< #define fill_err_hack 0
< #endif
<
< // in kernel. Workaround for cpu bug.
<
< // .macro hw_rei_spe
< // .iif eq spe_fix, hw_rei
< //#if spe_fix != 0
< //
< //
< //#define hw_rei_chm_count hw_rei_chm_count + 1
< // p4_fixup_label \hw_rei_chm_count
< // .iif eq build_fixed_image, br r31, hw_rei_update_spe
< // .iif ne build_fixed_image, hw_rei
< //#endif
< //
< // .endm
<
< // Add flag "osf_chm_fix" to enable dcache in user mode only
< // to avoid cpu bug.
<
< #ifndef osf_chm_fix
< // If set, enable D-Cache in
< #define osf_chm_fix 0
< #endif
<
< #if osf_chm_fix != 0
< // user mode only.
< #define hw_rei_chm_count 0
< #endif
<
< #if osf_chm_fix != 0
<
< #define hw_rei_stall_chm_count 0
< #endif
<
< #ifndef enable_p4_fixups
<
< #define enable_p4_fixups 0
< #endif
<
< // If set, do EV5 Pass 4 fixups
< #if spe_fix == 0
<
< #define osf_chm_fix 0
< #endif
<
< #if spe_fix == 0
<
< #define enable_p4_fixups 0
< #endif
<
< // Only allow fixups if fix enabled
<
< //Turn off fill_errors and MEM_NEM in user mode
< // .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_
< // //save r22,r23,r24
< // stqp r22, 0x150(r31) //add
< // stqp r23, 0x158(r31) //contents
< // stqp r24, 0x160(r31) //bit mask
< //
< // lda r22, 0x82(r31)
< // ldah r22, 0x8740(r22)
< // sll r22, 8, r22
< // ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK
< // bis r23,r31,r23
< //
< // lda r24, 0x8(r31) // r24 <- MEM_NEM bit
< // beq r10, L10_ // IF user mode (r10<0> == 0) pal mode
< // bic r23, r24, r23 // set fillerr_en bit
< // br r31, L20_ // ELSE
< //L10_: bis r23, r24, r23 // clear fillerr_en bit
< //L20_: // ENDIF
< //
< // stlp r23, 0x80(r22) // write back the CIA_MASK register
< // mb
< // ldlp r23, 0x80(r22)
< // bis r23,r31,r23
< // mb
< //
< // lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL
< // ldah r22, 0x8740(r22)
< // sll r22, 8, r22
< // ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL
< // bis r23,r31,r23
< //
< //
< // lda r24, 0x400(r31) // r9 <- fillerr_en bit
< // beq r10, L30_ // IF user mode (r10<0> == 0) pal mode
< // bic r23, r24, r23 // set fillerr_en bit
< // br r31, L40_ // ELSE
< //L30_: bis r23, r24, r23 // clear fillerr_en bit
< //L40_: // ENDIF
< //
< // stlp r23, 0(r22) // write back the CIA_CTRL register
< // mb
< // ldlp r23, 0(r22)
< // bis r23,r31,r23
< // mb
< //
< // //restore r22,r23,r24
< // ldqp r22, 0x150(r31)
< // ldqp r23, 0x158(r31)
< // ldqp r24, 0x160(r31)
< //
< // .endm
<
618a154
> #define max_cpuid 1
623,627c159
< #ifndef osf_svmin // platform specific palcode version number
< #define osf_svmin 0
< #endif
<
<
---
> #define osf_svmin 1
630,639c162,164
< // .mcall ldqp // override macro64 definition with macro from library
< // .mcall stqp // override macro64 definition with macro from library
<
<
< // .psect _pal,mix
< // huh pb pal_base:
< // huh pb #define current_block_base . - pal_base
<
< // .sbttl "RESET - Reset Trap Entry Point"
< //+
---
> //
> // RESET - Reset Trap Entry Point
> //
653c178
< //-
---
> //
656a182
> .globl _start
657a184
> _start:
662d188
< #ifdef SIMOS
667,668d192
< #else
< /* following is a srcmax change */
670,677d193
< DEBUGSTORE(0x41)
< /* The original code jumped using r1 as a linkage register to pass the base
< of PALcode to the platform specific code. We use r1 to pass a parameter
< from the SROM, so we hardcode the address of Pal_Base in platform.s
< */
< br r31, sys_reset
< #endif
<
689d204
< #if beh_model == 0
692,720c207,209
< #if enable_p4_fixups != 0
<
<
< .quad 0
< .long p4_fixup_hw_rei_fixup_table
< #endif
<
< #else
<
< .quad 0 //
< .quad 0 //0x0030
< .quad 0
< .quad 0 //0x0040
< .quad 0
< .quad 0 //0x0050
< .quad 0
< .quad 0 //0x0060
< .quad 0
< pal_enter_cns_address:
< .quad 0 //0x0070 -- address to jump to from enter_console
< .long <<sys_exit_console-pal_base>+1> //0x0078 -- offset to sys_exit_console (set palmode bit)
< #endif
<
<
<
<
< // .sbttl "IACCVIO- Istream Access Violation Trap Entry Point"
<
< //+
---
> //
> // IACCVIO - Istream Access Violation Trap Entry Point
> //
731c220
< //-
---
> //
777,779c266,268
< // .sbttl "INTERRUPT- Interrupt Trap Entry Point"
<
< //+
---
> //
> // INTERRUPT - Interrupt Trap Entry Point
> //
787,788c276,277
< // if necessary, switch to kernel mode
< // push stack frame, update ps (including current mode and ipl copies), sp, and gp
---
> // if necessary, switch to kernel mode push stack frame,
> // update ps (including current mode and ipl copies), sp, and gp
791,793c280
< //-
<
<
---
> //
840d326
< #ifdef SIMOS
847,853d332
< #else
< // Moved the following three lines to sys_interrupt to make room for debug
< // extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
< // mfpr r29, pt_kgp // update gp
<
< // mtpr r14, ev5__ipl // load the new IPL into Ibox
< #endif
858,860c337,339
< // .sbttl "ITBMISS- Istream TBmiss Trap Entry Point"
<
< //+
---
> //
> // ITBMISS - Istream TBmiss Trap Entry Point
> //
870c349
< //-
---
> //
874,891c353
< #if real_mm == 0
<
<
< // Simple 1-1 va->pa mapping
<
< nop // Pad to align to E1
< mfpr r8, exc_addr
<
< srl r8, page_offset_size_bits, r9
< sll r9, 32, r9
<
< lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
< mtpr r9, itb_pte // E1
<
< hw_rei_stall // Nital says I don't have to obey shadow wait rule here.
< #else
<
< // Real MM mapping
---
> // Real MM mapping
916d377
< #endif
918,923c379,381
<
<
<
< // .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point"
<
< //+
---
> //
> // DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point
> //
926c384,385
< // Vectored into via hardware trap on Dstream single translation buffer miss.
---
> // Vectored into via hardware trap on Dstream single translation
> // buffer miss.
932c391
< //-
---
> //
936,959d394
< #if real_mm == 0
< // Simple 1-1 va->pa mapping
< mfpr r8, va // E0
< srl r8, page_offset_size_bits, r9
<
< sll r9, 32, r9
< lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
<
< mtpr r9, dtb_pte // E0
< nop // Pad to align to E0
<
<
<
< mtpr r8, dtb_tag // E0
< nop
<
< nop // Pad tag write
< nop
<
< nop // Pad tag write
< nop
<
< hw_rei
< #else
987d421
< #endif
990,994c424,427
<
<
< // .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point"
<
< //+
---
> //
> // DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point
> //
> //
997c430,431
< // Vectored into via hardware trap on Double TBmiss from single miss flows.
---
> // Vectored into via hardware trap on Double TBmiss from single
> // miss flows.
1012c446
< //-
---
> //
1016d449
< #if ldvpte_bug_fix != 0
1021d453
< #endif
1036c468
< ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
---
> ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
1047c479
< ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
---
> ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
1066,1067c498,500
< // .sbttl "UNALIGN -- Dstream unalign trap"
< //+
---
> //
> // UNALIGN -- Dstream unalign trap
> //
1078c511
< //-
---
> //
1138,1142c571,573
<
<
< // .sbttl "DFAULT - Dstream Fault Trap Entry Point"
<
< //+
---
> //
> // DFAULT - Dstream Fault Trap Entry Point
> //
1145c576,577
< // Vectored into via hardware trap on dstream fault or sign check error on DVA.
---
> // Vectored into via hardware trap on dstream fault or sign check
> // error on DVA.
1156c588
< //-
---
> //
1203,1208c635,637
<
<
<
< // .sbttl "MCHK - Machine Check Trap Entry Point"
<
< //+
---
> //
> // MCHK - Machine Check Trap Entry Point
> //
1215c644
< //-
---
> //
1224,1228c653,655
<
<
< // .sbttl "OPCDEC - Illegal Opcode Trap Entry Point"
<
< //+
---
> //
> // OPCDEC - Illegal Opcode Trap Entry Point
> //
1239c666
< //-
---
> //
1287,1293c714,716
<
<
<
<
< // .sbttl "ARITH - Arithmetic Exception Trap Entry Point"
<
< //+
---
> //
> // ARITH - Arithmetic Exception Trap Entry Point
> //
1305c728
< //-
---
> //
1344c767
< srl r13, exc_sum_v_swc, r16// shift data to correct position
---
> srl r13, exc_sum_v_swc, r16 // shift data to correct position
1357,1363c780,782
<
<
<
<
< // .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point"
<
< //+
---
> //
> // FEN - Illegal Floating Point Operation Trap Entry Point
> //
1375c794
< //-
---
> //
1440,1443c859,864
< // .sbttl "Misc handlers"
< // Start area for misc code.
< //+
< //dfault_trap_cont
---
> //////////////////////////////////////////////////////////////////////////////
> // Misc handlers - Start area for misc code.
> //////////////////////////////////////////////////////////////////////////////
>
> //
> // dfault_trap_cont
1452c873
< //-
---
> //
1482c903
< //+
---
> //
1490c911
< //-
---
> //
1504c925
< //+
---
> //
1526c947
< //-
---
> //
1534,1535d954
< #if real_mm != 0
< // if not real_mm, should never get here from miss flows
1536a956,957
> // if not real_mm, should never get here from miss flows
>
1546d966
< #endif
1559d978
< //orig pvc_jsr updpcb, bsr=1
1571,1572c990
< ALIGN_BLOCK
< //+
---
> //
1578c996,997
< //-
---
> //
> ALIGN_BLOCK
1594c1013
< //+
---
> //
1598c1017
< //-
---
> //
1607,1609c1026,1027
< // .sbttl "Continuation of long call_pal flows"
< ALIGN_BLOCK
< //+
---
> // Continuation of long call_pal flows
> //
1615c1033,1034
< //-
---
> //
> ALIGN_BLOCK
1665c1084
< //+
---
> //
1669c1088
< //-
---
> //
1676,1681d1094
< #if icflush_on_tbix != 0
<
<
< br r31, pal_ic_flush // Flush Icache
< #else
<
1683d1095
< #endif
1692,1697d1103
< #if icflush_on_tbix != 0
<
<
< br r31, pal_ic_flush // Flush Icache
< #else
<
1699d1104
< #endif
1714d1118
< #if icflush_on_tbix != 0
1716,1717d1119
<
<
1719d1120
< br r31, pal_ic_flush_and_tbisi // Flush Icache
1721,1725d1121
< nop // Pad table
< #else
<
< nop
< nop
1728d1123
< #endif
1730,1731d1124
<
<
1744,1748d1136
< #if icflush_on_tbix != 0
<
<
< br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB
< #else
1754d1141
< #endif
1759c1146
< //+
---
> //
1762c1149
< //-
---
> //
1781c1168
< //+
---
> //
1784c1171
< //-
---
> //
1797c1184
< //+
---
> //
1800c1187
< //-
---
> //
1815c1202
< //+
---
> //
1818c1205
< //-
---
> //
1821d1207
< #if ev5_p1 != 0
1823,1840d1208
<
< bic r25, r24, r25 // clean icsr<FPE>
< get_impure r8 // get impure pointer
<
< sll r12, icsr_v_fpe, r12 // shift new fen to pos
< fix_impure_ipr r8 // adjust impure pointer
<
< restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits
< srl r23, 32, r24 // move asn to low asn pos
<
< ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
< srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
<
< or r25, r12, r25 // icsr with new fen
< sll r24, itb_asn_v_asn, r12
<
< #else
<
1844c1212
< ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
---
> ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr
1857d1224
< #endif
1868c1235
< ldqp r25, osfpcb_q_usp(r16) // get new usp
---
> ldq_p r25, osfpcb_q_usp(r16) // get new usp
1871c1238
< // pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
---
> // pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
1875c1242
< ldqp r30, osfpcb_q_ksp(r16) // get new ksp
---
> ldq_p r30, osfpcb_q_ksp(r16) // get new ksp
1877c1244
< // pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
---
> // pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
1880,1940d1246
< #if ev5_p1 != 0
<
<
< blbc r8, no_pm_change // if monitoring all processes -- no need to change pm
<
< // otherwise, monitoring select processes - update pm
< lda r25, 0x3F(r31)
< cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings
<
< sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask
< mfpr r22, ev5__pmctr
<
< and r8, r25, r8 // mask new ctl value
< bic r22, r25, r22 // clear ctl field in pmctr
<
< or r8, r22, r8
< mtpr r8, ev5__pmctr
<
< no_pm_change:
< #endif
<
<
< #if osf_chm_fix != 0
<
<
< p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here
<
< #if build_fixed_image != 0
<
<
< hw_rei_stall
< #else
<
< mfpr r9, pt_pcbb // get FEN
< #endif
<
< ldqp r9, osfpcb_q_fen(r9)
< blbc r9, no_pm_change_10_ // skip if FEN disabled
<
< mb // ensure no outstanding fills
< lda r12, 1<<dc_mode_v_dc_ena(r31)
< mtpr r12, dc_mode // turn dcache on so we can flush it
< nop // force correct slotting
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
<
< lda r8, 0(r31) // flood the dcache with junk data
< no_pm_change_5_: ldqp r31, 0(r8)
< lda r8, 0x20(r8) // touch each cache block
< srl r8, 13, r9
< blbc r9, no_pm_change_5_
<
< mb // ensure no outstanding fills
< mtpr r31, dc_mode // turn the dcache back off
< nop // force correct slotting
< mfpr r31, pt0 // no hw_rei_stall in 0,1
< #endif
<
<
1944c1250
< //+
---
> //
1946c1252
< //-
---
> //
1979c1285
< //+
---
> //
1991c1297
< //-
---
> //
2039c1345
< //+
---
> //
2050c1356
< //-
---
> //
2101c1407
< //+
---
> //
2114c1420
< //-
---
> //
2188d1493
< //+
2189a1495
> //
2195c1501
< //-
---
> //
2207c1513
< //+
---
> //
2225c1531
< //-
---
> //
2242c1548
< //+
---
> //
2248c1554
< //-
---
> //
2258c1564
< //+
---
> //
2262c1568
< //-
---
> //
2330,2332d1635
< #if icflush_on_tbix != 0
<
<
2334,2338d1636
<
< //+
< // Common Icache flush and ITB invalidate single routine.
< // ITBIS and hw_rei_stall must be in same octaword.
< // r17 - has address to invalidate
2340,2417d1637
< //-
< PAL_IC_FLUSH_AND_TBISI:
< nop
< mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
< nop
< nop
<
< // Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 10
<
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 20
<
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 30
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 40
<
<
< nop
< nop
<
< nop
< nop
<
< // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions
< // 44 nops plus 4 instructions before it is 48 instructions.
< // Since this routine started on a 32-byte (8 instruction) boundary,
< // the following 2 instructions will be in the same octword as required.
< // ALIGN_BRANCH
< mtpr r17, ev5__itb_is // Flush ITB
< hw_rei_stall
<
< #endif
<
< ALIGN_BLOCK
< //+
2427c1647
< //-
---
> //
2476c1696
< //+
---
> //
2481c1701
< //-
---
> //
2489c1709
< stqp r30, osfpcb_q_usp(r12) // store usp
---
> stq_p r30, osfpcb_q_usp(r12) // store usp
2491c1711
< pal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp
---
> pal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp
2495c1715
< stlp r14, osfpcb_l_cc(r12) // save time
---
> stl_p r14, osfpcb_l_cc(r12) // save time
2501,2505d1720
<
< #if remove_save_state == 0
<
< // .sbttl "PAL_SAVE_STATE"
< //+
2507c1722
< // Pal_save_state
---
> // pal_save_state
2528c1743
< //-
---
> //
2530d1744
<
2584,2585c1798
< mfpr r2, icsr // Get icsr //orig
< //orig ldah r0, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
---
> mfpr r2, icsr // Get icsr
2587,2588c1800,1801
< bic r2, r0, r0 // ICSR with SDE clear //orig
< mtpr r0, icsr // Turn off SDE //orig
---
> bic r2, r0, r0 // ICSR with SDE clear
> mtpr r0, icsr // Turn off SDE
2590,2593c1803,1806
< mfpr r31, pt0 // SDE bubble cycle 1 //orig
< mfpr r31, pt0 // SDE bubble cycle 2 //orig
< mfpr r31, pt0 // SDE bubble cycle 3 //orig
< nop //orig
---
> mfpr r31, pt0 // SDE bubble cycle 1
> mfpr r31, pt0 // SDE bubble cycle 2
> mfpr r31, pt0 // SDE bubble cycle 3
> nop
2597,2601d1809
< //orig #define t 4
< //orig .repeat 28
< //orig store_reg \t
< //orig #define t t + 1
< //orig .endr
2635,2639d1842
< //orig #define t 1
< //orig .repeat 23
< //orig store_reg \t , pal=1
< //orig #define t t + 1
< //orig .endr
2669,2671c1872,1874
< mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig
< mfpr r31, pt0 //orig
< mtpr r2, icsr // Restore original ICSR //orig
---
> mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write)
> mfpr r31, pt0
> mtpr r2, icsr // Restore original ICSR
2673,2676c1876,1879
< mfpr r31, pt0 // SDE bubble cycle 1 //orig
< mfpr r31, pt0 // SDE bubble cycle 2 //orig
< mfpr r31, pt0 // SDE bubble cycle 3 //orig
< nop //orig
---
> mfpr r31, pt0 // SDE bubble cycle 1
> mfpr r31, pt0 // SDE bubble cycle 2
> mfpr r31, pt0 // SDE bubble cycle 3
> nop
2679,2686d1881
<
< //orig #define t 8
< //orig .repeat 7
< //orig store_reg \t, shadow=1
< //orig #define t t + 1
< //orig .endr
< //orig store_reg 25, shadow=1
<
2696,2711d1890
< //orig store_reg exc_addr, ipr=1 // save ipr
< //orig store_reg pal_base, ipr=1 // save ipr
< //orig store_reg mm_stat, ipr=1 // save ipr
< //orig store_reg va, ipr=1 // save ipr
< //orig store_reg icsr, ipr=1 // save ipr
< //orig store_reg ipl, ipr=1 // save ipr
< //orig store_reg ps, ipr=1 // save ipr
< //orig store_reg itb_asn, ipr=1 // save ipr
< //orig store_reg aster, ipr=1 // save ipr
< //orig store_reg astrr, ipr=1 // save ipr
< //orig store_reg sirr, ipr=1 // save ipr
< //orig store_reg isr, ipr=1 // save ipr
< //orig store_reg ivptbr, ipr=1 // save ipr
< //orig store_reg mcsr, ipr=1 // save ipr
< //orig store_reg dc_mode, ipr=1 // save ipr
<
2737,2748d1915
< //orig store_reg icperr_stat, ipr=1
< //orig store_reg pmctr, ipr=1
< //orig store_reg intid, ipr=1
< //orig store_reg exc_sum, ipr=1
< //orig store_reg exc_mask, ipr=1
< //orig ldah r14, 0xfff0(r31)
< //orig zap r14, 0xE0, r14 // Get Cbox IPR base
< //orig nop // pad mf dcperr_stat out of shadow of last store
< //orig nop
< //orig nop
< //orig store_reg dcperr_stat, ipr=1
<
2763,2777d1929
< //orig mb
< //orig ldqp r2, ev5__sc_ctl(r14)
< //orig ldqp r13, ld_lock(r14)
< //orig ldqp r4, ev5__sc_addr(r14)
< //orig ldqp r5, ev5__ei_addr(r14)
< //orig ldqp r6, ev5__bc_tag_addr(r14)
< //orig ldqp r7, ev5__fill_syn(r14)
< //orig bis r5, r4, r31
< //orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them
< //orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr
< //orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn
< //orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked
< //orig mb
<
< #ifndef SIMOS
2791,2801d1942
< #endif
< //orig // save cbox ipr state
< //orig store_reg1 sc_ctl, r2, r1, ipr=1
< //orig store_reg1 ld_lock, r13, r1, ipr=1
< //orig store_reg1 sc_addr, r4, r1, ipr=1
< //orig store_reg1 ei_addr, r5, r1, ipr=1
< //orig store_reg1 bc_tag_addr, r6, r1, ipr=1
< //orig store_reg1 fill_syn, r7, r1, ipr=1
< //orig store_reg1 sc_stat, r8, r1, ipr=1
< //orig store_reg1 ei_stat, r9, r1, ipr=1
< //orig //bc_config? sl_rcv?
2802a1944
> // save cbox ipr state
2810a1953
> //bc_config? sl_rcv?
2812c1955
< // restore impure base //orig
---
> // restore impure base
2816,2819c1959,1961
< // save all floating regs //orig
< mfpr r0, icsr // get icsr //orig
< or r31, 1, r2 // get a one //orig
< //orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig
---
> // save all floating regs
> mfpr r0, icsr // get icsr
> or r31, 1, r2 // get a one
2821,2822c1963,1964
< or r2, r0, r0 // set FEN on //orig
< mtpr r0, icsr // write to icsr, enabling FEN //orig
---
> or r2, r0, r0 // set FEN on
> mtpr r0, icsr // write to icsr, enabling FEN
2825,2833d1966
< // orig mtpr r31, dtb_ia // clear the dtb
< // orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
< // orig sll r0, 32, r0 // shift to PFN field
< // orig lda r2, 0xff(r31) // all read enable and write enable bits set
< // orig sll r2, 8, r2 // move to PTE location
< // orig addq r0, r2, r0 // combine with PFN
< // orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< // orig mtpr r1, dtb_tag // write TB tag
<
2842,2851c1975
< //orig // map the next page too - in case the impure area crosses a page boundary
< //orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
< //orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
< //orig sll r0, 32, r0 // shift to PFN field
< //orig lda r2, 0xff(r31) // all read enable and write enable bits set
< //orig sll r2, 8, r2 // move to PTE location
< //orig addq r0, r2, r0 // combine with PFN
< //orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< //orig mtpr r4, dtb_tag // write TB tag
<
---
> // map the next page too - in case the impure area crosses a page boundary
2859,2862c1983,1986
< sll r31, 0, r31 // stall cycle 1 // orig
< sll r31, 0, r31 // stall cycle 2 // orig
< sll r31, 0, r31 // stall cycle 3 // orig
< nop // orig
---
> sll r31, 0, r31 // stall cycle 1
> sll r31, 0, r31 // stall cycle 2
> sll r31, 0, r31 // stall cycle 3
> nop
2864c1988
< //orig // add offset for saving fpr regs
---
> // add offset for saving fpr regs
2866d1989
<
2870,2876d1992
<
< //orig #define t 0
< //orig .repeat 32
< //orig store_reg \t , fpu=1
< //orig #define t t + 1
< //orig .endr
<
2912c2028
< //orig //switch impure offset from gpr to ipr---
---
> //switch impure offset from gpr to ipr---
2917c2033
< SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach// pb
---
> SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach
2920c2036
< //orig // and back to gpr ---
---
> // and back to gpr ---
2944c2060
< //orig // restore impure area base
---
> // restore impure area base
2948,2949c2064,2065
< mtpr r31, dtb_ia // clear the dtb //orig
< mtpr r31, itb_ia // clear the itb //orig
---
> mtpr r31, dtb_ia // clear the dtb
> mtpr r31, itb_ia // clear the itb
2953d2068
< #endif
2956d2070
< #if remove_restore_state == 0
2958d2071
<
2960d2072
< //+
2961a2074
> //
2975c2088
< //-
---
> //
2981,2992c2094
< //orig // map the console io area virtually
< //orig mtpr r31, dtb_ia // clear the dtb
< //orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
< //orig sll r0, 32, r0 // shift to PFN field
< //orig lda r2, 0xff(r31) // all read enable and write enable bits set
< //orig sll r2, 8, r2 // move to PTE location
< //orig addq r0, r2, r0 // combine with PFN
< //orig
< //orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< //orig mtpr r1, dtb_tag // write TB tag
< //orig
<
---
> // map the console io area virtually
3001,3011c2103
< //orig // map the next page too, in case impure area crosses page boundary
< //orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
< //orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
< //orig sll r0, 32, r0 // shift to PFN field
< //orig lda r2, 0xff(r31) // all read enable and write enable bits set
< //orig sll r2, 8, r2 // move to PTE location
< //orig addq r0, r2, r0 // combine with PFN
< //orig
< //orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< //orig mtpr r4, dtb_tag // write TB tag - no virtual mbox instruction for 3 cycles
<
---
> // map the next page too, in case impure area crosses page boundary
3019,3026c2111
< //orig // save all floating regs
< //orig mfpr r0, icsr // get icsr
< //orig// assume ICSR_V_SDE gt <ICSR_V_FPE> // assertion checker
< //orig or r31, <<1@<ICSR_V_SDE-ICSR_V_FPE>> ! 1>, r2 // set SDE and FPE
< //orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot
< //orig or r2, r0, r0 // set FEN on
< //orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr.
<
---
> // save all floating regs
3044,3051d2128
< //orig
< //orig // restore all floating regs
< //orig#define t 0
< //orig .repeat 32
< //orig restore_reg \t , fpu=1
< //orig#define t t + 1
< //orig .endr
<
3056a2134,2135
>
> // restore all floating regs
3090c2169
< //orig // switch impure pointer from gpr to ipr area --
---
> // switch impure pointer from gpr to ipr area --
3093,3100d2171
< //orig
< //orig // restore all pal regs
< //orig#define t 1
< //orig .repeat 23
< //orig restore_reg \t , pal=1
< //orig#define t t + 1
< //orig .endr
<
3102a2174,2175
>
> // restore all pal regs
3176,3183d2248
< //orig#define t 8
< //orig .repeat 7
< //orig restore_reg \t, shadow=1
< //orig#define t t + 1
< //orig .endr
< //orig restore_reg 25, shadow=1
< //orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles
<
3198,3204c2263,2268
< mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig
< mfpr r31, pt0 // "" //orig
< mfpr r0, icsr // Get icsr //orig
< //orig ldah r2, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
< ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig
< bic r0, r2, r2 // ICSR with SDE clear //orig
< mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig
---
> mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway)
> mfpr r31, pt0 // ""
> mfpr r0, icsr // Get icsr
> ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location
> bic r0, r2, r2 // ICSR with SDE clear
> mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles
3206,3209c2270,2273
< mfpr r31, pt0 // SDE bubble cycle 1 //orig
< mfpr r31, pt0 // SDE bubble cycle 2 //orig
< mfpr r31, pt0 // SDE bubble cycle 3 //orig
< nop //orig
---
> mfpr r31, pt0 // SDE bubble cycle 1
> mfpr r31, pt0 // SDE bubble cycle 2
> mfpr r31, pt0 // SDE bubble cycle 3
> nop
3211c2275
< //orig // switch impure pointer from ipr to gpr area --
---
> // switch impure pointer from ipr to gpr area --
3214,3219d2277
< //orig // restore all integer regs
< //orig#define t 4
< //orig .repeat 28
< //orig restore_reg \t
< //orig#define t t + 1
< //orig .endr
3225a2284
> // restore all integer regs
3287c2346
< mfpr r31, pt0 // stall for ldqp above //orig
---
> mfpr r31, pt0 // stall for ldq_p above //orig
3294d2352
< #endif
3297c2355
< //+
---
> //
3315c2373
< //-
---
> //
3364d2421
< // align_to_call_pal_section // Align to address of first call_pal entry point - 2000
3366d2422
< // .sbttl "HALT - PALcode for HALT instruction"
3368c2424,2426
< //+
---
> // align_to_call_pal_section
> // Align to address of first call_pal entry point - 2000
>
3369a2428,2429
> // HALT - PALcode for HALT instruction
> //
3376c2436
< //-
---
> //
3382d2441
< #if rax_mode == 0
3397,3419d2455
< #else // RAX mode
< mb
< mb
< mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles.
< mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles.
< mtpr r8, exc_addr // no HW_REI for 1 cycle.
< blbc r9, not_begin_case
< mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles.
< mtpr r31, ev5__itb_ia // clear ITB.
<
< not_begin_case:
< nop
< nop
<
< nop
< nop // pad mt itb_asn ->hw_rei_stall
<
< hw_rei_stall
< #endif
<
< // .sbttl "CFLUSH- PALcode for CFLUSH instruction"
<
< //+
3420a2457,2458
> // CFLUSH - PALcode for CFLUSH instruction
> //
3430c2468
< //-
---
> //
3436,3437d2473
< // .sbttl "DRAINA - PALcode for DRAINA instruction"
< //+
3438a2475,2476
> // DRAINA - PALcode for DRAINA instruction
> //
3448c2486
< //-
---
> //
3470c2508
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
3496,3497d2533
< // .sbttl "CSERVE- PALcode for CSERVE instruction"
< //+
3498a2535,2536
> // CSERVE - PALcode for CSERVE instruction
> //
3509c2547
< //-
---
> //
3515,3517d2552
< // .sbttl "swppal - PALcode for swppal instruction"
<
< //+
3518a2554,2555
> // swppal - PALcode for swppal instruction
> //
3533c2570
< //-
---
> //
3554c2591
< CALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr
---
> CALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr
3577,3578d2613
< // .sbttl "wripir- PALcode for wripir instruction"
< //+
3579a2615,2616
> // wripir - PALcode for wripir instruction
> //
3591c2628
< //-
---
> //
3607,3609d2643
< // .sbttl "rdmces- PALcode for rdmces instruction"
<
< //+
3610a2645,2646
> // rdmces - PALcode for rdmces instruction
> //
3616c2652
< //-
---
> //
3625,3627d2660
< // .sbttl "wrmces- PALcode for wrmces instruction"
<
< //+
3628a2662,2663
> // wrmces - PALcode for wrmces instruction
> //
3639c2674
< //-
---
> //
3655d2689
< #if rawhide_system == 0
3657,3659d2690
< #else
< blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock
< #endif
3666c2697
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
3768,3770d2798
< // .sbttl "wrfen - PALcode for wrfen instruction"
<
< //+
3771a2800,2801
> // wrfen - PALcode for wrfen instruction
> //
3778c2808,2809
< // Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE
---
> // Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16)
> // are UNPREDICTABLE
3781c2812
< //-
---
> //
3798c2829
< stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB.
---
> stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB.
3812,3813d2842
< // .sbttl "wrvptpr - PALcode for wrvptpr instruction"
< //+
3814a2844,2845
> // wrvptpr - PALcode for wrvptpr instruction
> //
3820c2851
< //-
---
> //
3838d2868
< // .sbttl "swpctx- PALcode for swpctx instruction"
3840d2869
< //+
3841a2871,2872
> // swpctx - PALcode for swpctx instruction
> //
3853c2884
< //-
---
> //
3860,3861c2891,2892
< ldqp r22, osfpcb_q_fen(r16) // get new fen/pme
< ldqp r23, osfpcb_l_cc(r16) // get new asn
---
> ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme
> ldq_p r23, osfpcb_l_cc(r16) // get new asn
3866,3867c2897,2898
< stqp r30, osfpcb_q_ksp(r0) // store old ksp
< // pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow.
---
> stq_p r30, osfpcb_q_ksp(r0) // store old ksp
> // pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow.
3870c2901
< stqp r24, osfpcb_q_usp(r0) // store usp
---
> stq_p r24, osfpcb_q_usp(r0) // store usp
3873c2904
< stlp r25, osfpcb_l_cc(r0) // save time
---
> stl_p r25, osfpcb_l_cc(r0) // save time
3879c2910
< ev5_pass2 lda r24, (1<<icsr_v_pmp)(r24)
---
> lda r24, (1<<icsr_v_pmp)(r24)
3882,3883d2912
< // .sbttl "wrval - PALcode for wrval instruction"
< //+
3884a2914,2915
> // wrval - PALcode for wrval instruction
> //
3890c2921
< //-
---
> //
3900,3903d2930
<
< // .sbttl "rdval - PALcode for rdval instruction"
<
< //+
3904a2932,2933
> // rdval - PALcode for rdval instruction
> //
3910c2939
< //-
---
> //
3919,3920d2947
< // .sbttl "tbi - PALcode for tbi instruction"
< //+
3921a2949,2950
> // tbi - PALcode for tbi instruction
> //
3929c2958
< //-
---
> //
3949,3950d2977
< // .sbttl "wrent - PALcode for wrent instruction"
< //+
3951a2979,2980
> // wrent - PALcode for wrent instruction
> //
3961c2990
< //-
---
> //
3981,3982d3009
< // .sbttl "swpipl - PALcode for swpipl instruction"
< //+
3983a3011,3012
> // swpipl - PALcode for swpipl instruction
> //
3992c3021
< //-
---
> //
4010,4011d3038
< // .sbttl "rdps - PALcode for rdps instruction"
< //+
4012a3040,3041
> // rdps - PALcode for rdps instruction
> //
4018c3047
< //-
---
> //
4026,4027d3054
< // .sbttl "wrkgp - PALcode for wrkgp instruction"
< //+
4028a3056,3057
> // wrkgp - PALcode for wrkgp instruction
> //
4034c3063
< //-
---
> //
4044,4045d3072
< // .sbttl "wrusp - PALcode for wrusp instruction"
< //+
4046a3074,3075
> // wrusp - PALcode for wrusp instruction
> //
4052c3081
< //-
---
> //
4062,4063d3090
< // .sbttl "wrperfmon - PALcode for wrperfmon instruction"
< //+
4064a3092,3093
> // wrperfmon - PALcode for wrperfmon instruction
> //
4140d3168
< #if perfmon_debug == 0
4165d3192
< #else
4167,4171d3193
< br r31, pal_perfmon_debug
< #endif
<
< // .sbttl "rdusp - PALcode for rdusp instruction"
< //+
4172a3195,3196
> // rdusp - PALcode for rdusp instruction
> //
4178c3202
< //-
---
> //
4191,4192d3214
< // .sbttl "whami - PALcode for whami instruction"
< //+
4193a3216,3217
> // whami - PALcode for whami instruction
> //
4199c3223
< //-
---
> //
4207d3230
< // .sbttl "retsys - PALcode for retsys instruction"
4208a3232,3233
> // retsys - PALcode for retsys instruction
> //
4219c3244
< //-
---
> //
4253,4254d3277
< // .sbttl "rti - PALcode for rti instruction"
< //+
4255a3279,3280
> // rti - PALcode for rti instruction
> //
4266c3291
< //-
---
> //
4269d3293
< #ifdef SIMOS
4272d3295
< #endif
4299,4301c3322,3325
< // .sbttl "Start the Unprivileged CALL_PAL Entry Points"
< // .sbttl "bpt- PALcode for bpt instruction"
< //+
---
> ///////////////////////////////////////////////////
> // Start the Unprivileged CALL_PAL Entry Points
> ///////////////////////////////////////////////////
>
4302a3327,3328
> // bpt - PALcode for bpt instruction
> //
4313d3338
< //-
4314a3340
> //
4343,4344d3368
< // .sbttl "bugchk- PALcode for bugchk instruction"
< //+
4345a3370,3371
> // bugchk - PALcode for bugchk instruction
> //
4356d3381
< //-
4357a3383
> //
4388,4389d3413
< // .sbttl "callsys - PALcode for callsys instruction"
< //+
4390a3415,3416
> // callsys - PALcode for callsys instruction
> //
4400d3425
< //-
4401a3427
> //
4411c3437
< //+
---
> //
4413c3439
< //-
---
> //
4443,4444d3468
< // .sbttl "imb - PALcode for imb instruction"
< //+
4445a3470,3471
> // imb - PALcode for imb instruction
> //
4452d3477
< //-
4453a3479
> //
4463c3489
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
4557,4558d3582
< // .sbttl "rdunique - PALcode for rdunique instruction"
< //+
4559a3584,3585
> // rdunique - PALcode for rdunique instruction
> //
4566d3591
< //-
4567a3593
> //
4571c3597
< ldqp r0, osfpcb_q_unique(r0) // get new value
---
> ldq_p r0, osfpcb_q_unique(r0) // get new value
4575,4576d3600
< // .sbttl "wrunique - PALcode for wrunique instruction"
< //+
4577a3602,3603
> // wrunique - PALcode for wrunique instruction
> //
4584d3609
< //-
4585a3611
> //
4590c3616
< stqp r16, osfpcb_q_unique(r12)// get new value
---
> stq_p r16, osfpcb_q_unique(r12)// get new value
4594c3620
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
4637,4638c3663,3665
< // .sbttl "gentrap - PALcode for gentrap instruction"
< //+
---
> //
> // gentrap - PALcode for gentrap instruction
> //
4650c3677
< //-
---
> //
4679c3706
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
4776c3803
< // .sbttl "Continuation of MTPR_PERFMON"
---
> // Continuation of MTPR_PERFMON
4778d3804
< #if perfmon_debug == 0
4807c3833
< stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
---
> stq_p r25, ev5__bc_ctl(r14) // store to cbox ipr
4878c3904
< ldqp r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
---
> ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
4885d3910
< //orig sget_addr r12, 1<<icsr_v_pmp, r31
4890c3915
< ev5_pass2 mtpr r13, icsr // update icsr
---
> mtpr r13, icsr // update icsr
4892,4895d3916
< #if ev5_p1 != 0
< lda r12, 1(r31)
< cmovlbc r25, r12, r16 // r16<0> set if either pme=1 or sprocess=0 (sprocess in bit 0 of r25)
< #else
4897d3917
< #endif
4985c4005
< //orig get_addr r8, (1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk), r31 // build mode mask for pmctr register
---
> // build mode mask for pmctr register
4993c4013,4014
< //;the following code will only be used in pass2, but should not hurt anything if run in pass1.
---
> // the following code will only be used in pass2, but should
> // not hurt anything if run in pass1.
4999c4020
< ev5_pass2 mtpr r8, icsr // 4 bubbles to hw_rei
---
> mtpr r8, icsr // 4 bubbles to hw_rei
5003c4024,4025
< //;the following code not needed for pass2 and later, but should work anyway.
---
> // the following code not needed for pass2 and later, but
> // should work anyway.
5021c4043
< // I guess this should be a shift of 4 bits from the above control register structure .. pb
---
> // I guess this should be a shift of 4 bits from the above control register structure
5046,5047c4068
< //orig get_addr r9, 0xFFFFFFFF, r31, verify=0 // ctr2<15:0>,ctr1<15:0> mask
< LDLI(r9, (0xFFFFFFFF))
---
> LDLI(r9, (0xFFFFFFFF)) // ctr2<15:0>,ctr1<15:0> mask
5065d4085
< #else
5067c4087,4089
< // end of "real code", start of debug code
---
> //////////////////////////////////////////////////////////
> // Copy code
> //////////////////////////////////////////////////////////
5069,5178d4090
< //+
< // Debug environment:
< // (in pass2, always set icsr<pma> to ensure master counter enable is on)
< // R16 = 0 Write to on-chip performance monitor ipr
< // r17 = on-chip ipr
< // r0 = return value of read of on-chip performance monitor ipr
< // R16 = 1 Setup Cbox mux selects
< // r17 = Cbox mux selects in same position as in bc_ctl ipr.
< // r0 = return value of read of on-chip performance monitor ipr
< //
< //-
< pal_perfmon_debug:
< mfpr r8, icsr
< lda r9, 1<<icsr_v_pma(r31)
< bis r8, r9, r8
< mtpr r8, icsr
<
< mfpr r0, ev5__pmctr // read old value
< bne r16, cbox_mux_sel
<
< mtpr r17, ev5__pmctr // update pmctr ipr
< br r31, end_pm
<
< cbox_mux_sel:
< // ok, now tackle cbox mux selects
< ldah r14, 0xfff0(r31)
< zap r14, 0xE0, r14 // Get Cbox IPR base
< //orig get_bc_ctl_shadow r16 // bc_ctl returned
< mfpr r16, pt_impure
< lda r16, CNS_Q_IPR(r16)
< RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
<
< lda r8, 0x3F(r31) // build mux select mask
< sll r8, BC_CTL_V_PM_MUX_SEL, r8
<
< and r17, r8, r25 // isolate bc_ctl mux select bits
< bic r16, r8, r16 // isolate old mux select bits
< or r16, r25, r25 // create new bc_ctl
< mb // clear out cbox for future ipr write
< stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
< mb // clear out cbox for future ipr write
< //orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
< mfpr r16, pt_impure
< lda r16, CNS_Q_IPR(r16)
< SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
<
< end_pm: hw_rei
<
< #endif
<
<
< //;The following code is a workaround for a cpu bug where Istream prefetches to
< //;super-page address space in user mode may escape off-chip.
< #if spe_fix != 0
<
< ALIGN_BLOCK
< hw_rei_update_spe:
< mfpr r12, pt_misc // get previous mode
< srl r11, osfps_v_mode, r10 // isolate current mode bit
< and r10, 1, r10
< extbl r12, 7, r8 // get previous mode field
< and r8, 1, r8 // isolate previous mode bit
< cmpeq r10, r8, r8 // compare previous and current modes
< beq r8, hw_rei_update_spe_5_
< hw_rei // if same, just return
<
< hw_rei_update_spe_5_:
<
< #if fill_err_hack != 0
<
< fill_error_hack
< #endif
<
< mfpr r8, icsr // get current icsr value
< ldah r9, (2<<(icsr_v_spe-16))(r31) // get spe bit mask
< bic r8, r9, r8 // disable spe
< xor r10, 1, r9 // flip mode for new spe bit
< sll r9, icsr_v_spe+1, r9 // shift into position
< bis r8, r9, r8 // enable/disable spe
< lda r9, 1(r31) // now update our flag
< sll r9, pt_misc_v_cm, r9 // previous mode saved bit mask
< bic r12, r9, r12 // clear saved previous mode
< sll r10, pt_misc_v_cm, r9 // current mode saved bit mask
< bis r12, r9, r12 // set saved current mode
< mtpr r12, pt_misc // update pt_misc
< mtpr r8, icsr // update icsr
<
< #if osf_chm_fix != 0
<
<
< blbc r10, hw_rei_update_spe_10_ // branch if not user mode
<
< mb // ensure no outstanding fills
< lda r12, 1<<dc_mode_v_dc_ena(r31) // User mode
< mtpr r12, dc_mode // Turn on dcache
< mtpr r31, dc_flush // and flush it
< br r31, pal_ic_flush
<
< hw_rei_update_spe_10_: mfpr r9, pt_pcbb // Kernel mode
< ldqp r9, osfpcb_q_Fen(r9) // get FEN
< blbc r9, pal_ic_flush // return if FP disabled
< mb // ensure no outstanding fills
< mtpr r31, dc_mode // turn off dcache
< #endif
<
<
< br r31, pal_ic_flush // Pal restriction - must flush Icache if changing ICSR<SPE>
< #endif
<
<
5181c4093,4112
< ble r18, finished #if len <=0 we are finished
---
> #ifdef CACHE_COPY
> #ifndef CACHE_COPY_UNALIGNED
> and r16, 63, r8
> and r17, 63, r9
> bis r8, r9, r8
> bne r8, cache_copy_done
> #endif
> bic r18, 63, r8
> and r18, 63, r18
> beq r8, cache_copy_done
> cache_loop:
> ldf f17, 0(r16)
> stf f17, 0(r16)
> addq r17, 64, r17
> addq r16, 64, r16
> subq r8, 64, r8
> bne r8, cache_loop
> cache_copy_done:
> #endif
> ble r18, finished // if len <=0 we are finished
< Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development Company, L.P.
---
> * Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development
> * Company, L.P.
> *
> * Permission is hereby granted, free of charge, to any person
> * obtaining a copy of this software and associated documentation
> * files (the "Software"), to deal in the Software without
> * restriction, including without limitation the rights to use, copy,
> * modify, merge, publish, distribute, sublicense, and/or sell copies
> * of the Software, and to permit persons to whom the Software is
> * furnished to do so, subject to the following conditions:
> *
> * The above copyright notice and this permission notice shall be
> * included in all copies or substantial portions of the Software.
> *
> * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> * SOFTWARE.
> */
35,53d56
< Permission is hereby granted, free of charge, to any person obtaining a copy of
< this software and associated documentation files (the "Software"), to deal in
< the Software without restriction, including without limitation the rights to
< use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
< of the Software, and to permit persons to whom the Software is furnished to do
< so, subject to the following conditions:
<
< The above copyright notice and this permission notice shall be included in all
< copies or substantial portions of the Software.
<
< THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
< IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
< FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
< AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
< LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
< OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
< SOFTWARE.
< */
<
56,61d58
<
< // build_fixed_image: not sure what means
< // real_mm to be replaced during rewrite
< // remove_save_state remove_restore_state can be remooved to save space ??
<
<
71d67
< #ifdef SIMOS
73,77d68
< #else
< #define DEBUGSTORE(c) \
< lda r13, c(zero) ; \
< bsr r25, debugstore
< #endif
84,112c75,76
< #define egore 0
< #define acore 0
< #define beh_model 0
< #define ev5_p2 1
< #define ev5_p1 0
< #define ldvpte_bug_fix 1
< #define osf_chm_fix 0
<
< // Do we want to do this?? pb
< #define spe_fix 0
< // Do we want to do this?? pb
< #define build_fixed_image 0
<
< #define ev5_pass2
< #define enable_p4_fixups 0
< #define osf_svmin 1
< #define enable_physical_console 0
< #define fill_err_hack 0
< #define icflush_on_tbix 0
< #define max_cpuid 1
< #define perfmon_debug 0
< #define rawhide_system 0
< #define rax_mode 0
<
<
< // This is the fix for the user-mode super page references causing the machine to crash.
< #if (spe_fix == 1) && (build_fixed_image==1)
< #define hw_rei_spe br r31, hw_rei_update_spe
< #else
---
> // This is the fix for the user-mode super page references causing the
> // machine to crash.
114d77
< #endif
116,315d78
<
< // redefine a few of the distribution-code names to match the Hudson gas names.
< // opcodes
< #define ldqp ldq_p
< #define stqp stq_p
< #define ldlp ldl_p
< #define stlp stl_p
<
< #define r0 $0
< #define r1 $1
< #define r2 $2
< #define r3 $3
< #define r4 $4
< #define r5 $5
< #define r6 $6
< #define r7 $7
< #define r8 $8
< #define r9 $9
< #define r10 $10
< #define r11 $11
< #define r12 $12
< #define r13 $13
< #define r14 $14
< #define r15 $15
< #define r16 $16
< #define r17 $17
< #define r18 $18
< #define r19 $19
< #define r20 $20
< #define r21 $21
< #define r22 $22
< #define r23 $23
< #define r24 $24
< #define r25 $25
< #define r26 $26
< #define r27 $27
< #define r28 $28
< #define r29 $29
< #define r30 $30
< #define r31 $31
<
< // .title "EV5 OSF PAL"
< // .ident "V1.18"
< //
< //****************************************************************************
< //* *
< //* Copyright (c) 1992, 1993, 1994, 1995 *
< //* by DIGITAL Equipment Corporation, Maynard, Mass. *
< //* *
< //* This software is furnished under a license and may be used and copied *
< //* only in accordance with the terms of such license and with the *
< //* inclusion of the above copyright notice. This software or any other *
< //* copies thereof may not be provided or otherwise made available to any *
< //* other person. No title to and ownership of the software is hereby *
< //* transferred. *
< //* *
< //* The information in this software is subject to change without notice *
< //* and should not be construed as a commitment by DIGITAL Equipment *
< //* Corporation. *
< //* *
< //* DIGITAL assumes no responsibility for the use or reliability of its *
< //* software on equipment which is not supplied by DIGITAL. *
< //* *
< //****************************************************************************
<
< // .sbttl "Edit History"
< //+
< // Who Rev When What
< // ------------ --- ----------- --------------------------------
< // DB 0.0 03-Nov-1992 Start
< // DB 0.1 28-Dec-1992 add swpctx
< // DB 0.2 05-Jan-1993 Bug: PVC found mtpr dtb_CM -> virt ref bug
< // DB 0.3 11-Jan-1993 rearrange trap entry points
< // DB 0.4 01-Feb-1993 add tbi
< // DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal
< // DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14)
< // DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC
< // Bug: typo on register number for store in wrunique
< // Bug: rti to kern uses r16 as scratch
< // Bug: callsys saving wrong value in pt_usp
< // DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp
< // DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice
< // Bug: rti stl_c could corrupt the stack
< // Bug: unaligned returning wrong value in r17 (or should be and)
< // DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt
< // DB 0.11 23-Feb-1993 Turn caches on in reset flow
< // DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow
< // DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses
< // DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS
< // DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES
< // DB 0.16 12-May-1993 Update reset
< // New restriction: no mfpr exc_addr in cycle 1 of call_pal flows
< // Bug: in wrmces, not clearing DPC, DSC
< // Update swppal
< // Add pal bugchecks, pal_save_state, pal_restore_state
< // DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps.
< // New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn
< // DB 0.18 26-May-1993 PVC fixes
< // JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores
< // JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl
< // Bug: exc_addr was being loaded before stores that could dtb_miss in the following
< // routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN
< // JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines:
< // TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN::
< // dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler:
< // osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN::
< // Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles
< // JM 0.22 28-jul-1993 Add WRIPIR instruction
< // JM 0.23 05-aug-1993 Bump version number for release
< // JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation
< // JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals;
< // New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode),
< // and SWPCTX
< // JM 0.26 07-oct-1993 Re-implement pal_version
< // JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM
< // JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush
< // JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead
< // of mm_stat<opcode>. mm_stat contains original opcode, not hw_ld.
< // JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys
< // JM 0.31 15-nov-1993 BUG: WRFEN trashing r0
< // JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0
< // JM 0.33 24-nov-1993 save/restore_state -
< // BUG: use ivptbr to restore mvptbr
< // BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit
< // CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors
< // JM 0.34 20-dec-1993 BUG: set r11<mode> to kernel for ksnv halt case
< // BUG: generate ksnv halt when tb miss on kernel stack accesses
< // save exc_addr in r14 for invalid_dpte stack builder
< // JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in
< // the same shadow
< // JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS
< // New palcode restiction: mt icsr<fpe,hwe> --> 3 bubbles to hw_rei --affects wrfen
< // JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions
< // Hide impure area manipulations in macros
< // BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st
< // Add some pvc_violate statements
< // JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality;
< // Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments
< // Add code to ensure fen bit set in icsr before ldt
< // conditionally compile rax_more_reset out.
< // move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here
< // move rax reset stuff to ev5_osf_system_pal.m64
< // JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow
< // and performance monitoring bits
< // Change to save_state routine to save more iprs.
< // JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in
< // JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems)
< // remove_save_state,remove_restore_state;fix new pvc violation in save_state
< // JM 0.42 22-feb-1994 BUG: save_state overwriting r3
< // JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr
< // JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions
< // JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem)
< // New pal restriction in pal_restore_state: icsr<fpe>->floating instr = 3 bubbles
< // Add exc_sum and exc_mask to pal_save_state (not restore)
< // JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure
< // area.
< // Add performance counter support to swpctx and wrperfmon
< // JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix)
< // JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts
< // JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is
< // taken in the interrupt flow, stack is pushed twice.
< // SWPPAL - update to support ECO 59 to allow 0 as a valid address
< // Add itb flush to save/restore state routines
< // Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but
< // conforms to itbia restriction.
< // Added enable_physical_console flag (for enter/exit console routines only)
< // JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a
< // load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and
< // nmiss_fetch_err to nmiss_fetch_ldr31_err.
< // JM 1.00 1-aug-1994 Add pass2 support (swpctx)
< // JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2
< // JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2)
< // Moved perfmon code here from system file.
< // BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1)
< // JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit.
< // JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change
< // after ISR read, but we won't catch the ISR update. reverse order
< // JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31
< // JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code)
< // JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to
< // DTBMISS_SINGLE if not in palmode.
< // JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame
< // JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox
< // superpage mode in User mode and re-enable in kernel mode.
< // EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this.
< // JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2
< // ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid
< // cpu bug.
< // JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state
< // ES 1.13 17-mar-1995 Refine osf_chm_fix
< // ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix
< // ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state
< // Force pvc checking of exit_console
< // ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0
< // ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting)
< // instead of xor to maintain previous mode in pt_misc
< // ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does
< // not have pme set. The bits in icsr maintain the master enable state.
< // In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable
< //
322d84
< //-
324d85
< // .sbttl "PALtemp register usage"
326c87,90
< //+
---
> ///////////////////////////
> // PALtemp register usage
> ///////////////////////////
>
346c110,111
< // pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces
---
> // pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami,
> // pt_mces
355c120
< //-
---
> //
357c122,126
< // .sbttl "PALshadow register usage"
---
>
> /////////////////////////////
> // PALshadow register usage
> /////////////////////////////
>
359,360d127
< //+
< //
373,374d139
< //
< //-
376,387d140
< // .sbttl "ALPHA symbol definitions"
< // _OSF_PSDEF GLOBAL
< // _OSF_PTEDEF GLOBAL
< // _OSF_VADEF GLOBAL
< // _OSF_PCBDEF GLOBAL
< // _OSF_SFDEF GLOBAL
< // _OSF_MMCSR_DEF GLOBAL
< // _SCBDEF GLOBAL
< // _FRMDEF GLOBAL
< // _EXSDEF GLOBAL
< // _OSF_A0_DEF GLOBAL
< // _MCESDEF GLOBAL
389d141
< // .sbttl "EV5 symbol definitions"
391,405d142
< // _EV5DEF
< // _PALTEMP
< // _MM_STAT_DEF
< // _EV5_MM
< // _EV5_IPLDEF
<
< // _HALT_CODES GLOBAL
< // _MCHK_CODES GLOBAL
<
< // _PAL_IMPURE
< // _PAL_LOGOUT
<
<
<
<
413,614d149
<
< #define osfpal 1 // This is the PALcode for OSF.
<
< #ifndef rawhide_system
<
< #define rawhide_system 0
< #endif
<
<
< #ifndef real_mm
< // Page table translation vs 1-1 mapping
< #define real_mm 1
< #endif
<
<
< #ifndef rax_mode
<
< #define rax_mode 0
< #endif
<
< #ifndef egore
< // End of reset flow starts a program at 200000(hex).
< #define egore 1
< #endif
<
< #ifndef acore
< // End of reset flow starts a program at 40000(hex).
< #define acore 0
< #endif
<
<
< // assume acore+egore+rax_mode lt 2 // Assertion checker
<
< #ifndef beh_model
< // EV5 behavioral model specific code
< #define beh_model 1
< #endif
<
< #ifndef init_cbox
< // Reset flow init of Bcache and Scache
< #define init_cbox 1
< #endif
<
< #ifndef disable_crd
< // Decides whether the reset flow will disable
< #define disable_crd 0
< #endif
<
< // correctable read interrupts via ICSR
< #ifndef perfmon_debug
< #define perfmon_debug 0
< #endif
<
< #ifndef icflush_on_tbix
< #define icflush_on_tbix 0
< #endif
<
< #ifndef remove_restore_state
< #define remove_restore_state 0
< #endif
<
< #ifndef remove_save_state
< #define remove_save_state 0
< #endif
<
< #ifndef enable_physical_console
< #define enable_physical_console 0
< #endif
<
< #ifndef ev5_p1
< #define ev5_p1 0
< #endif
<
< #ifndef ev5_p2
< #define ev5_p2 1
< #endif
<
< // assume ev5_p1+ev5_p2 eq 1
<
< #ifndef ldvpte_bug_fix
< #define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow.
< #endif
<
< #ifndef spe_fix
< // If set, disable super-page mode in user mode and re-enable
< #define spe_fix 0
< #endif
< // in kernel. Workaround for cpu bug.
< #ifndef build_fixed_image
< #define build_fixed_image 0
< #endif
<
<
< #ifndef fill_err_hack
< // If set, disable fill_error mode in user mode and re-enable
< #define fill_err_hack 0
< #endif
<
< // in kernel. Workaround for cpu bug.
<
< // .macro hw_rei_spe
< // .iif eq spe_fix, hw_rei
< //#if spe_fix != 0
< //
< //
< //#define hw_rei_chm_count hw_rei_chm_count + 1
< // p4_fixup_label \hw_rei_chm_count
< // .iif eq build_fixed_image, br r31, hw_rei_update_spe
< // .iif ne build_fixed_image, hw_rei
< //#endif
< //
< // .endm
<
< // Add flag "osf_chm_fix" to enable dcache in user mode only
< // to avoid cpu bug.
<
< #ifndef osf_chm_fix
< // If set, enable D-Cache in
< #define osf_chm_fix 0
< #endif
<
< #if osf_chm_fix != 0
< // user mode only.
< #define hw_rei_chm_count 0
< #endif
<
< #if osf_chm_fix != 0
<
< #define hw_rei_stall_chm_count 0
< #endif
<
< #ifndef enable_p4_fixups
<
< #define enable_p4_fixups 0
< #endif
<
< // If set, do EV5 Pass 4 fixups
< #if spe_fix == 0
<
< #define osf_chm_fix 0
< #endif
<
< #if spe_fix == 0
<
< #define enable_p4_fixups 0
< #endif
<
< // Only allow fixups if fix enabled
<
< //Turn off fill_errors and MEM_NEM in user mode
< // .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_
< // //save r22,r23,r24
< // stqp r22, 0x150(r31) //add
< // stqp r23, 0x158(r31) //contents
< // stqp r24, 0x160(r31) //bit mask
< //
< // lda r22, 0x82(r31)
< // ldah r22, 0x8740(r22)
< // sll r22, 8, r22
< // ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK
< // bis r23,r31,r23
< //
< // lda r24, 0x8(r31) // r24 <- MEM_NEM bit
< // beq r10, L10_ // IF user mode (r10<0> == 0) pal mode
< // bic r23, r24, r23 // set fillerr_en bit
< // br r31, L20_ // ELSE
< //L10_: bis r23, r24, r23 // clear fillerr_en bit
< //L20_: // ENDIF
< //
< // stlp r23, 0x80(r22) // write back the CIA_MASK register
< // mb
< // ldlp r23, 0x80(r22)
< // bis r23,r31,r23
< // mb
< //
< // lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL
< // ldah r22, 0x8740(r22)
< // sll r22, 8, r22
< // ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL
< // bis r23,r31,r23
< //
< //
< // lda r24, 0x400(r31) // r9 <- fillerr_en bit
< // beq r10, L30_ // IF user mode (r10<0> == 0) pal mode
< // bic r23, r24, r23 // set fillerr_en bit
< // br r31, L40_ // ELSE
< //L30_: bis r23, r24, r23 // clear fillerr_en bit
< //L40_: // ENDIF
< //
< // stlp r23, 0(r22) // write back the CIA_CTRL register
< // mb
< // ldlp r23, 0(r22)
< // bis r23,r31,r23
< // mb
< //
< // //restore r22,r23,r24
< // ldqp r22, 0x150(r31)
< // ldqp r23, 0x158(r31)
< // ldqp r24, 0x160(r31)
< //
< // .endm
<
618a154
> #define max_cpuid 1
623,627c159
< #ifndef osf_svmin // platform specific palcode version number
< #define osf_svmin 0
< #endif
<
<
---
> #define osf_svmin 1
630,639c162,164
< // .mcall ldqp // override macro64 definition with macro from library
< // .mcall stqp // override macro64 definition with macro from library
<
<
< // .psect _pal,mix
< // huh pb pal_base:
< // huh pb #define current_block_base . - pal_base
<
< // .sbttl "RESET - Reset Trap Entry Point"
< //+
---
> //
> // RESET - Reset Trap Entry Point
> //
653c178
< //-
---
> //
656a182
> .globl _start
657a184
> _start:
662d188
< #ifdef SIMOS
667,668d192
< #else
< /* following is a srcmax change */
670,677d193
< DEBUGSTORE(0x41)
< /* The original code jumped using r1 as a linkage register to pass the base
< of PALcode to the platform specific code. We use r1 to pass a parameter
< from the SROM, so we hardcode the address of Pal_Base in platform.s
< */
< br r31, sys_reset
< #endif
<
689d204
< #if beh_model == 0
692,720c207,209
< #if enable_p4_fixups != 0
<
<
< .quad 0
< .long p4_fixup_hw_rei_fixup_table
< #endif
<
< #else
<
< .quad 0 //
< .quad 0 //0x0030
< .quad 0
< .quad 0 //0x0040
< .quad 0
< .quad 0 //0x0050
< .quad 0
< .quad 0 //0x0060
< .quad 0
< pal_enter_cns_address:
< .quad 0 //0x0070 -- address to jump to from enter_console
< .long <<sys_exit_console-pal_base>+1> //0x0078 -- offset to sys_exit_console (set palmode bit)
< #endif
<
<
<
<
< // .sbttl "IACCVIO- Istream Access Violation Trap Entry Point"
<
< //+
---
> //
> // IACCVIO - Istream Access Violation Trap Entry Point
> //
731c220
< //-
---
> //
777,779c266,268
< // .sbttl "INTERRUPT- Interrupt Trap Entry Point"
<
< //+
---
> //
> // INTERRUPT - Interrupt Trap Entry Point
> //
787,788c276,277
< // if necessary, switch to kernel mode
< // push stack frame, update ps (including current mode and ipl copies), sp, and gp
---
> // if necessary, switch to kernel mode push stack frame,
> // update ps (including current mode and ipl copies), sp, and gp
791,793c280
< //-
<
<
---
> //
840d326
< #ifdef SIMOS
847,853d332
< #else
< // Moved the following three lines to sys_interrupt to make room for debug
< // extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
< // mfpr r29, pt_kgp // update gp
<
< // mtpr r14, ev5__ipl // load the new IPL into Ibox
< #endif
858,860c337,339
< // .sbttl "ITBMISS- Istream TBmiss Trap Entry Point"
<
< //+
---
> //
> // ITBMISS - Istream TBmiss Trap Entry Point
> //
870c349
< //-
---
> //
874,891c353
< #if real_mm == 0
<
<
< // Simple 1-1 va->pa mapping
<
< nop // Pad to align to E1
< mfpr r8, exc_addr
<
< srl r8, page_offset_size_bits, r9
< sll r9, 32, r9
<
< lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
< mtpr r9, itb_pte // E1
<
< hw_rei_stall // Nital says I don't have to obey shadow wait rule here.
< #else
<
< // Real MM mapping
---
> // Real MM mapping
916d377
< #endif
918,923c379,381
<
<
<
< // .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point"
<
< //+
---
> //
> // DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point
> //
926c384,385
< // Vectored into via hardware trap on Dstream single translation buffer miss.
---
> // Vectored into via hardware trap on Dstream single translation
> // buffer miss.
932c391
< //-
---
> //
936,959d394
< #if real_mm == 0
< // Simple 1-1 va->pa mapping
< mfpr r8, va // E0
< srl r8, page_offset_size_bits, r9
<
< sll r9, 32, r9
< lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
<
< mtpr r9, dtb_pte // E0
< nop // Pad to align to E0
<
<
<
< mtpr r8, dtb_tag // E0
< nop
<
< nop // Pad tag write
< nop
<
< nop // Pad tag write
< nop
<
< hw_rei
< #else
987d421
< #endif
990,994c424,427
<
<
< // .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point"
<
< //+
---
> //
> // DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point
> //
> //
997c430,431
< // Vectored into via hardware trap on Double TBmiss from single miss flows.
---
> // Vectored into via hardware trap on Double TBmiss from single
> // miss flows.
1012c446
< //-
---
> //
1016d449
< #if ldvpte_bug_fix != 0
1021d453
< #endif
1036c468
< ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
---
> ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
1047c479
< ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
---
> ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
1066,1067c498,500
< // .sbttl "UNALIGN -- Dstream unalign trap"
< //+
---
> //
> // UNALIGN -- Dstream unalign trap
> //
1078c511
< //-
---
> //
1138,1142c571,573
<
<
< // .sbttl "DFAULT - Dstream Fault Trap Entry Point"
<
< //+
---
> //
> // DFAULT - Dstream Fault Trap Entry Point
> //
1145c576,577
< // Vectored into via hardware trap on dstream fault or sign check error on DVA.
---
> // Vectored into via hardware trap on dstream fault or sign check
> // error on DVA.
1156c588
< //-
---
> //
1203,1208c635,637
<
<
<
< // .sbttl "MCHK - Machine Check Trap Entry Point"
<
< //+
---
> //
> // MCHK - Machine Check Trap Entry Point
> //
1215c644
< //-
---
> //
1224,1228c653,655
<
<
< // .sbttl "OPCDEC - Illegal Opcode Trap Entry Point"
<
< //+
---
> //
> // OPCDEC - Illegal Opcode Trap Entry Point
> //
1239c666
< //-
---
> //
1287,1293c714,716
<
<
<
<
< // .sbttl "ARITH - Arithmetic Exception Trap Entry Point"
<
< //+
---
> //
> // ARITH - Arithmetic Exception Trap Entry Point
> //
1305c728
< //-
---
> //
1344c767
< srl r13, exc_sum_v_swc, r16// shift data to correct position
---
> srl r13, exc_sum_v_swc, r16 // shift data to correct position
1357,1363c780,782
<
<
<
<
< // .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point"
<
< //+
---
> //
> // FEN - Illegal Floating Point Operation Trap Entry Point
> //
1375c794
< //-
---
> //
1440,1443c859,864
< // .sbttl "Misc handlers"
< // Start area for misc code.
< //+
< //dfault_trap_cont
---
> //////////////////////////////////////////////////////////////////////////////
> // Misc handlers - Start area for misc code.
> //////////////////////////////////////////////////////////////////////////////
>
> //
> // dfault_trap_cont
1452c873
< //-
---
> //
1482c903
< //+
---
> //
1490c911
< //-
---
> //
1504c925
< //+
---
> //
1526c947
< //-
---
> //
1534,1535d954
< #if real_mm != 0
< // if not real_mm, should never get here from miss flows
1536a956,957
> // if not real_mm, should never get here from miss flows
>
1546d966
< #endif
1559d978
< //orig pvc_jsr updpcb, bsr=1
1571,1572c990
< ALIGN_BLOCK
< //+
---
> //
1578c996,997
< //-
---
> //
> ALIGN_BLOCK
1594c1013
< //+
---
> //
1598c1017
< //-
---
> //
1607,1609c1026,1027
< // .sbttl "Continuation of long call_pal flows"
< ALIGN_BLOCK
< //+
---
> // Continuation of long call_pal flows
> //
1615c1033,1034
< //-
---
> //
> ALIGN_BLOCK
1665c1084
< //+
---
> //
1669c1088
< //-
---
> //
1676,1681d1094
< #if icflush_on_tbix != 0
<
<
< br r31, pal_ic_flush // Flush Icache
< #else
<
1683d1095
< #endif
1692,1697d1103
< #if icflush_on_tbix != 0
<
<
< br r31, pal_ic_flush // Flush Icache
< #else
<
1699d1104
< #endif
1714d1118
< #if icflush_on_tbix != 0
1716,1717d1119
<
<
1719d1120
< br r31, pal_ic_flush_and_tbisi // Flush Icache
1721,1725d1121
< nop // Pad table
< #else
<
< nop
< nop
1728d1123
< #endif
1730,1731d1124
<
<
1744,1748d1136
< #if icflush_on_tbix != 0
<
<
< br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB
< #else
1754d1141
< #endif
1759c1146
< //+
---
> //
1762c1149
< //-
---
> //
1781c1168
< //+
---
> //
1784c1171
< //-
---
> //
1797c1184
< //+
---
> //
1800c1187
< //-
---
> //
1815c1202
< //+
---
> //
1818c1205
< //-
---
> //
1821d1207
< #if ev5_p1 != 0
1823,1840d1208
<
< bic r25, r24, r25 // clean icsr<FPE>
< get_impure r8 // get impure pointer
<
< sll r12, icsr_v_fpe, r12 // shift new fen to pos
< fix_impure_ipr r8 // adjust impure pointer
<
< restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits
< srl r23, 32, r24 // move asn to low asn pos
<
< ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
< srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
<
< or r25, r12, r25 // icsr with new fen
< sll r24, itb_asn_v_asn, r12
<
< #else
<
1844c1212
< ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
---
> ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr
1857d1224
< #endif
1868c1235
< ldqp r25, osfpcb_q_usp(r16) // get new usp
---
> ldq_p r25, osfpcb_q_usp(r16) // get new usp
1871c1238
< // pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
---
> // pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
1875c1242
< ldqp r30, osfpcb_q_ksp(r16) // get new ksp
---
> ldq_p r30, osfpcb_q_ksp(r16) // get new ksp
1877c1244
< // pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
---
> // pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
1880,1940d1246
< #if ev5_p1 != 0
<
<
< blbc r8, no_pm_change // if monitoring all processes -- no need to change pm
<
< // otherwise, monitoring select processes - update pm
< lda r25, 0x3F(r31)
< cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings
<
< sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask
< mfpr r22, ev5__pmctr
<
< and r8, r25, r8 // mask new ctl value
< bic r22, r25, r22 // clear ctl field in pmctr
<
< or r8, r22, r8
< mtpr r8, ev5__pmctr
<
< no_pm_change:
< #endif
<
<
< #if osf_chm_fix != 0
<
<
< p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here
<
< #if build_fixed_image != 0
<
<
< hw_rei_stall
< #else
<
< mfpr r9, pt_pcbb // get FEN
< #endif
<
< ldqp r9, osfpcb_q_fen(r9)
< blbc r9, no_pm_change_10_ // skip if FEN disabled
<
< mb // ensure no outstanding fills
< lda r12, 1<<dc_mode_v_dc_ena(r31)
< mtpr r12, dc_mode // turn dcache on so we can flush it
< nop // force correct slotting
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
< mfpr r31, pt0 // no mbox instructions in 1,2,3,4
<
< lda r8, 0(r31) // flood the dcache with junk data
< no_pm_change_5_: ldqp r31, 0(r8)
< lda r8, 0x20(r8) // touch each cache block
< srl r8, 13, r9
< blbc r9, no_pm_change_5_
<
< mb // ensure no outstanding fills
< mtpr r31, dc_mode // turn the dcache back off
< nop // force correct slotting
< mfpr r31, pt0 // no hw_rei_stall in 0,1
< #endif
<
<
1944c1250
< //+
---
> //
1946c1252
< //-
---
> //
1979c1285
< //+
---
> //
1991c1297
< //-
---
> //
2039c1345
< //+
---
> //
2050c1356
< //-
---
> //
2101c1407
< //+
---
> //
2114c1420
< //-
---
> //
2188d1493
< //+
2189a1495
> //
2195c1501
< //-
---
> //
2207c1513
< //+
---
> //
2225c1531
< //-
---
> //
2242c1548
< //+
---
> //
2248c1554
< //-
---
> //
2258c1564
< //+
---
> //
2262c1568
< //-
---
> //
2330,2332d1635
< #if icflush_on_tbix != 0
<
<
2334,2338d1636
<
< //+
< // Common Icache flush and ITB invalidate single routine.
< // ITBIS and hw_rei_stall must be in same octaword.
< // r17 - has address to invalidate
2340,2417d1637
< //-
< PAL_IC_FLUSH_AND_TBISI:
< nop
< mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
< nop
< nop
<
< // Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 10
<
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 20
<
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 30
< nop
< nop
< nop
< nop
<
< nop
< nop
< nop
< nop
<
< nop
< nop // 40
<
<
< nop
< nop
<
< nop
< nop
<
< // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions
< // 44 nops plus 4 instructions before it is 48 instructions.
< // Since this routine started on a 32-byte (8 instruction) boundary,
< // the following 2 instructions will be in the same octword as required.
< // ALIGN_BRANCH
< mtpr r17, ev5__itb_is // Flush ITB
< hw_rei_stall
<
< #endif
<
< ALIGN_BLOCK
< //+
2427c1647
< //-
---
> //
2476c1696
< //+
---
> //
2481c1701
< //-
---
> //
2489c1709
< stqp r30, osfpcb_q_usp(r12) // store usp
---
> stq_p r30, osfpcb_q_usp(r12) // store usp
2491c1711
< pal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp
---
> pal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp
2495c1715
< stlp r14, osfpcb_l_cc(r12) // save time
---
> stl_p r14, osfpcb_l_cc(r12) // save time
2501,2505d1720
<
< #if remove_save_state == 0
<
< // .sbttl "PAL_SAVE_STATE"
< //+
2507c1722
< // Pal_save_state
---
> // pal_save_state
2528c1743
< //-
---
> //
2530d1744
<
2584,2585c1798
< mfpr r2, icsr // Get icsr //orig
< //orig ldah r0, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
---
> mfpr r2, icsr // Get icsr
2587,2588c1800,1801
< bic r2, r0, r0 // ICSR with SDE clear //orig
< mtpr r0, icsr // Turn off SDE //orig
---
> bic r2, r0, r0 // ICSR with SDE clear
> mtpr r0, icsr // Turn off SDE
2590,2593c1803,1806
< mfpr r31, pt0 // SDE bubble cycle 1 //orig
< mfpr r31, pt0 // SDE bubble cycle 2 //orig
< mfpr r31, pt0 // SDE bubble cycle 3 //orig
< nop //orig
---
> mfpr r31, pt0 // SDE bubble cycle 1
> mfpr r31, pt0 // SDE bubble cycle 2
> mfpr r31, pt0 // SDE bubble cycle 3
> nop
2597,2601d1809
< //orig #define t 4
< //orig .repeat 28
< //orig store_reg \t
< //orig #define t t + 1
< //orig .endr
2635,2639d1842
< //orig #define t 1
< //orig .repeat 23
< //orig store_reg \t , pal=1
< //orig #define t t + 1
< //orig .endr
2669,2671c1872,1874
< mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig
< mfpr r31, pt0 //orig
< mtpr r2, icsr // Restore original ICSR //orig
---
> mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write)
> mfpr r31, pt0
> mtpr r2, icsr // Restore original ICSR
2673,2676c1876,1879
< mfpr r31, pt0 // SDE bubble cycle 1 //orig
< mfpr r31, pt0 // SDE bubble cycle 2 //orig
< mfpr r31, pt0 // SDE bubble cycle 3 //orig
< nop //orig
---
> mfpr r31, pt0 // SDE bubble cycle 1
> mfpr r31, pt0 // SDE bubble cycle 2
> mfpr r31, pt0 // SDE bubble cycle 3
> nop
2679,2686d1881
<
< //orig #define t 8
< //orig .repeat 7
< //orig store_reg \t, shadow=1
< //orig #define t t + 1
< //orig .endr
< //orig store_reg 25, shadow=1
<
2696,2711d1890
< //orig store_reg exc_addr, ipr=1 // save ipr
< //orig store_reg pal_base, ipr=1 // save ipr
< //orig store_reg mm_stat, ipr=1 // save ipr
< //orig store_reg va, ipr=1 // save ipr
< //orig store_reg icsr, ipr=1 // save ipr
< //orig store_reg ipl, ipr=1 // save ipr
< //orig store_reg ps, ipr=1 // save ipr
< //orig store_reg itb_asn, ipr=1 // save ipr
< //orig store_reg aster, ipr=1 // save ipr
< //orig store_reg astrr, ipr=1 // save ipr
< //orig store_reg sirr, ipr=1 // save ipr
< //orig store_reg isr, ipr=1 // save ipr
< //orig store_reg ivptbr, ipr=1 // save ipr
< //orig store_reg mcsr, ipr=1 // save ipr
< //orig store_reg dc_mode, ipr=1 // save ipr
<
2737,2748d1915
< //orig store_reg icperr_stat, ipr=1
< //orig store_reg pmctr, ipr=1
< //orig store_reg intid, ipr=1
< //orig store_reg exc_sum, ipr=1
< //orig store_reg exc_mask, ipr=1
< //orig ldah r14, 0xfff0(r31)
< //orig zap r14, 0xE0, r14 // Get Cbox IPR base
< //orig nop // pad mf dcperr_stat out of shadow of last store
< //orig nop
< //orig nop
< //orig store_reg dcperr_stat, ipr=1
<
2763,2777d1929
< //orig mb
< //orig ldqp r2, ev5__sc_ctl(r14)
< //orig ldqp r13, ld_lock(r14)
< //orig ldqp r4, ev5__sc_addr(r14)
< //orig ldqp r5, ev5__ei_addr(r14)
< //orig ldqp r6, ev5__bc_tag_addr(r14)
< //orig ldqp r7, ev5__fill_syn(r14)
< //orig bis r5, r4, r31
< //orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them
< //orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr
< //orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn
< //orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked
< //orig mb
<
< #ifndef SIMOS
2791,2801d1942
< #endif
< //orig // save cbox ipr state
< //orig store_reg1 sc_ctl, r2, r1, ipr=1
< //orig store_reg1 ld_lock, r13, r1, ipr=1
< //orig store_reg1 sc_addr, r4, r1, ipr=1
< //orig store_reg1 ei_addr, r5, r1, ipr=1
< //orig store_reg1 bc_tag_addr, r6, r1, ipr=1
< //orig store_reg1 fill_syn, r7, r1, ipr=1
< //orig store_reg1 sc_stat, r8, r1, ipr=1
< //orig store_reg1 ei_stat, r9, r1, ipr=1
< //orig //bc_config? sl_rcv?
2802a1944
> // save cbox ipr state
2810a1953
> //bc_config? sl_rcv?
2812c1955
< // restore impure base //orig
---
> // restore impure base
2816,2819c1959,1961
< // save all floating regs //orig
< mfpr r0, icsr // get icsr //orig
< or r31, 1, r2 // get a one //orig
< //orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig
---
> // save all floating regs
> mfpr r0, icsr // get icsr
> or r31, 1, r2 // get a one
2821,2822c1963,1964
< or r2, r0, r0 // set FEN on //orig
< mtpr r0, icsr // write to icsr, enabling FEN //orig
---
> or r2, r0, r0 // set FEN on
> mtpr r0, icsr // write to icsr, enabling FEN
2825,2833d1966
< // orig mtpr r31, dtb_ia // clear the dtb
< // orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
< // orig sll r0, 32, r0 // shift to PFN field
< // orig lda r2, 0xff(r31) // all read enable and write enable bits set
< // orig sll r2, 8, r2 // move to PTE location
< // orig addq r0, r2, r0 // combine with PFN
< // orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< // orig mtpr r1, dtb_tag // write TB tag
<
2842,2851c1975
< //orig // map the next page too - in case the impure area crosses a page boundary
< //orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
< //orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
< //orig sll r0, 32, r0 // shift to PFN field
< //orig lda r2, 0xff(r31) // all read enable and write enable bits set
< //orig sll r2, 8, r2 // move to PTE location
< //orig addq r0, r2, r0 // combine with PFN
< //orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< //orig mtpr r4, dtb_tag // write TB tag
<
---
> // map the next page too - in case the impure area crosses a page boundary
2859,2862c1983,1986
< sll r31, 0, r31 // stall cycle 1 // orig
< sll r31, 0, r31 // stall cycle 2 // orig
< sll r31, 0, r31 // stall cycle 3 // orig
< nop // orig
---
> sll r31, 0, r31 // stall cycle 1
> sll r31, 0, r31 // stall cycle 2
> sll r31, 0, r31 // stall cycle 3
> nop
2864c1988
< //orig // add offset for saving fpr regs
---
> // add offset for saving fpr regs
2866d1989
<
2870,2876d1992
<
< //orig #define t 0
< //orig .repeat 32
< //orig store_reg \t , fpu=1
< //orig #define t t + 1
< //orig .endr
<
2912c2028
< //orig //switch impure offset from gpr to ipr---
---
> //switch impure offset from gpr to ipr---
2917c2033
< SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach// pb
---
> SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach
2920c2036
< //orig // and back to gpr ---
---
> // and back to gpr ---
2944c2060
< //orig // restore impure area base
---
> // restore impure area base
2948,2949c2064,2065
< mtpr r31, dtb_ia // clear the dtb //orig
< mtpr r31, itb_ia // clear the itb //orig
---
> mtpr r31, dtb_ia // clear the dtb
> mtpr r31, itb_ia // clear the itb
2953d2068
< #endif
2956d2070
< #if remove_restore_state == 0
2958d2071
<
2960d2072
< //+
2961a2074
> //
2975c2088
< //-
---
> //
2981,2992c2094
< //orig // map the console io area virtually
< //orig mtpr r31, dtb_ia // clear the dtb
< //orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
< //orig sll r0, 32, r0 // shift to PFN field
< //orig lda r2, 0xff(r31) // all read enable and write enable bits set
< //orig sll r2, 8, r2 // move to PTE location
< //orig addq r0, r2, r0 // combine with PFN
< //orig
< //orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< //orig mtpr r1, dtb_tag // write TB tag
< //orig
<
---
> // map the console io area virtually
3001,3011c2103
< //orig // map the next page too, in case impure area crosses page boundary
< //orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
< //orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
< //orig sll r0, 32, r0 // shift to PFN field
< //orig lda r2, 0xff(r31) // all read enable and write enable bits set
< //orig sll r2, 8, r2 // move to PTE location
< //orig addq r0, r2, r0 // combine with PFN
< //orig
< //orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
< //orig mtpr r4, dtb_tag // write TB tag - no virtual mbox instruction for 3 cycles
<
---
> // map the next page too, in case impure area crosses page boundary
3019,3026c2111
< //orig // save all floating regs
< //orig mfpr r0, icsr // get icsr
< //orig// assume ICSR_V_SDE gt <ICSR_V_FPE> // assertion checker
< //orig or r31, <<1@<ICSR_V_SDE-ICSR_V_FPE>> ! 1>, r2 // set SDE and FPE
< //orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot
< //orig or r2, r0, r0 // set FEN on
< //orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr.
<
---
> // save all floating regs
3044,3051d2128
< //orig
< //orig // restore all floating regs
< //orig#define t 0
< //orig .repeat 32
< //orig restore_reg \t , fpu=1
< //orig#define t t + 1
< //orig .endr
<
3056a2134,2135
>
> // restore all floating regs
3090c2169
< //orig // switch impure pointer from gpr to ipr area --
---
> // switch impure pointer from gpr to ipr area --
3093,3100d2171
< //orig
< //orig // restore all pal regs
< //orig#define t 1
< //orig .repeat 23
< //orig restore_reg \t , pal=1
< //orig#define t t + 1
< //orig .endr
<
3102a2174,2175
>
> // restore all pal regs
3176,3183d2248
< //orig#define t 8
< //orig .repeat 7
< //orig restore_reg \t, shadow=1
< //orig#define t t + 1
< //orig .endr
< //orig restore_reg 25, shadow=1
< //orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles
<
3198,3204c2263,2268
< mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig
< mfpr r31, pt0 // "" //orig
< mfpr r0, icsr // Get icsr //orig
< //orig ldah r2, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
< ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig
< bic r0, r2, r2 // ICSR with SDE clear //orig
< mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig
---
> mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway)
> mfpr r31, pt0 // ""
> mfpr r0, icsr // Get icsr
> ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location
> bic r0, r2, r2 // ICSR with SDE clear
> mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles
3206,3209c2270,2273
< mfpr r31, pt0 // SDE bubble cycle 1 //orig
< mfpr r31, pt0 // SDE bubble cycle 2 //orig
< mfpr r31, pt0 // SDE bubble cycle 3 //orig
< nop //orig
---
> mfpr r31, pt0 // SDE bubble cycle 1
> mfpr r31, pt0 // SDE bubble cycle 2
> mfpr r31, pt0 // SDE bubble cycle 3
> nop
3211c2275
< //orig // switch impure pointer from ipr to gpr area --
---
> // switch impure pointer from ipr to gpr area --
3214,3219d2277
< //orig // restore all integer regs
< //orig#define t 4
< //orig .repeat 28
< //orig restore_reg \t
< //orig#define t t + 1
< //orig .endr
3225a2284
> // restore all integer regs
3287c2346
< mfpr r31, pt0 // stall for ldqp above //orig
---
> mfpr r31, pt0 // stall for ldq_p above //orig
3294d2352
< #endif
3297c2355
< //+
---
> //
3315c2373
< //-
---
> //
3364d2421
< // align_to_call_pal_section // Align to address of first call_pal entry point - 2000
3366d2422
< // .sbttl "HALT - PALcode for HALT instruction"
3368c2424,2426
< //+
---
> // align_to_call_pal_section
> // Align to address of first call_pal entry point - 2000
>
3369a2428,2429
> // HALT - PALcode for HALT instruction
> //
3376c2436
< //-
---
> //
3382d2441
< #if rax_mode == 0
3397,3419d2455
< #else // RAX mode
< mb
< mb
< mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles.
< mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles.
< mtpr r8, exc_addr // no HW_REI for 1 cycle.
< blbc r9, not_begin_case
< mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles.
< mtpr r31, ev5__itb_ia // clear ITB.
<
< not_begin_case:
< nop
< nop
<
< nop
< nop // pad mt itb_asn ->hw_rei_stall
<
< hw_rei_stall
< #endif
<
< // .sbttl "CFLUSH- PALcode for CFLUSH instruction"
<
< //+
3420a2457,2458
> // CFLUSH - PALcode for CFLUSH instruction
> //
3430c2468
< //-
---
> //
3436,3437d2473
< // .sbttl "DRAINA - PALcode for DRAINA instruction"
< //+
3438a2475,2476
> // DRAINA - PALcode for DRAINA instruction
> //
3448c2486
< //-
---
> //
3470c2508
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
3496,3497d2533
< // .sbttl "CSERVE- PALcode for CSERVE instruction"
< //+
3498a2535,2536
> // CSERVE - PALcode for CSERVE instruction
> //
3509c2547
< //-
---
> //
3515,3517d2552
< // .sbttl "swppal - PALcode for swppal instruction"
<
< //+
3518a2554,2555
> // swppal - PALcode for swppal instruction
> //
3533c2570
< //-
---
> //
3554c2591
< CALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr
---
> CALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr
3577,3578d2613
< // .sbttl "wripir- PALcode for wripir instruction"
< //+
3579a2615,2616
> // wripir - PALcode for wripir instruction
> //
3591c2628
< //-
---
> //
3607,3609d2643
< // .sbttl "rdmces- PALcode for rdmces instruction"
<
< //+
3610a2645,2646
> // rdmces - PALcode for rdmces instruction
> //
3616c2652
< //-
---
> //
3625,3627d2660
< // .sbttl "wrmces- PALcode for wrmces instruction"
<
< //+
3628a2662,2663
> // wrmces - PALcode for wrmces instruction
> //
3639c2674
< //-
---
> //
3655d2689
< #if rawhide_system == 0
3657,3659d2690
< #else
< blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock
< #endif
3666c2697
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
3768,3770d2798
< // .sbttl "wrfen - PALcode for wrfen instruction"
<
< //+
3771a2800,2801
> // wrfen - PALcode for wrfen instruction
> //
3778c2808,2809
< // Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE
---
> // Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16)
> // are UNPREDICTABLE
3781c2812
< //-
---
> //
3798c2829
< stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB.
---
> stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB.
3812,3813d2842
< // .sbttl "wrvptpr - PALcode for wrvptpr instruction"
< //+
3814a2844,2845
> // wrvptpr - PALcode for wrvptpr instruction
> //
3820c2851
< //-
---
> //
3838d2868
< // .sbttl "swpctx- PALcode for swpctx instruction"
3840d2869
< //+
3841a2871,2872
> // swpctx - PALcode for swpctx instruction
> //
3853c2884
< //-
---
> //
3860,3861c2891,2892
< ldqp r22, osfpcb_q_fen(r16) // get new fen/pme
< ldqp r23, osfpcb_l_cc(r16) // get new asn
---
> ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme
> ldq_p r23, osfpcb_l_cc(r16) // get new asn
3866,3867c2897,2898
< stqp r30, osfpcb_q_ksp(r0) // store old ksp
< // pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow.
---
> stq_p r30, osfpcb_q_ksp(r0) // store old ksp
> // pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow.
3870c2901
< stqp r24, osfpcb_q_usp(r0) // store usp
---
> stq_p r24, osfpcb_q_usp(r0) // store usp
3873c2904
< stlp r25, osfpcb_l_cc(r0) // save time
---
> stl_p r25, osfpcb_l_cc(r0) // save time
3879c2910
< ev5_pass2 lda r24, (1<<icsr_v_pmp)(r24)
---
> lda r24, (1<<icsr_v_pmp)(r24)
3882,3883d2912
< // .sbttl "wrval - PALcode for wrval instruction"
< //+
3884a2914,2915
> // wrval - PALcode for wrval instruction
> //
3890c2921
< //-
---
> //
3900,3903d2930
<
< // .sbttl "rdval - PALcode for rdval instruction"
<
< //+
3904a2932,2933
> // rdval - PALcode for rdval instruction
> //
3910c2939
< //-
---
> //
3919,3920d2947
< // .sbttl "tbi - PALcode for tbi instruction"
< //+
3921a2949,2950
> // tbi - PALcode for tbi instruction
> //
3929c2958
< //-
---
> //
3949,3950d2977
< // .sbttl "wrent - PALcode for wrent instruction"
< //+
3951a2979,2980
> // wrent - PALcode for wrent instruction
> //
3961c2990
< //-
---
> //
3981,3982d3009
< // .sbttl "swpipl - PALcode for swpipl instruction"
< //+
3983a3011,3012
> // swpipl - PALcode for swpipl instruction
> //
3992c3021
< //-
---
> //
4010,4011d3038
< // .sbttl "rdps - PALcode for rdps instruction"
< //+
4012a3040,3041
> // rdps - PALcode for rdps instruction
> //
4018c3047
< //-
---
> //
4026,4027d3054
< // .sbttl "wrkgp - PALcode for wrkgp instruction"
< //+
4028a3056,3057
> // wrkgp - PALcode for wrkgp instruction
> //
4034c3063
< //-
---
> //
4044,4045d3072
< // .sbttl "wrusp - PALcode for wrusp instruction"
< //+
4046a3074,3075
> // wrusp - PALcode for wrusp instruction
> //
4052c3081
< //-
---
> //
4062,4063d3090
< // .sbttl "wrperfmon - PALcode for wrperfmon instruction"
< //+
4064a3092,3093
> // wrperfmon - PALcode for wrperfmon instruction
> //
4140d3168
< #if perfmon_debug == 0
4165d3192
< #else
4167,4171d3193
< br r31, pal_perfmon_debug
< #endif
<
< // .sbttl "rdusp - PALcode for rdusp instruction"
< //+
4172a3195,3196
> // rdusp - PALcode for rdusp instruction
> //
4178c3202
< //-
---
> //
4191,4192d3214
< // .sbttl "whami - PALcode for whami instruction"
< //+
4193a3216,3217
> // whami - PALcode for whami instruction
> //
4199c3223
< //-
---
> //
4207d3230
< // .sbttl "retsys - PALcode for retsys instruction"
4208a3232,3233
> // retsys - PALcode for retsys instruction
> //
4219c3244
< //-
---
> //
4253,4254d3277
< // .sbttl "rti - PALcode for rti instruction"
< //+
4255a3279,3280
> // rti - PALcode for rti instruction
> //
4266c3291
< //-
---
> //
4269d3293
< #ifdef SIMOS
4272d3295
< #endif
4299,4301c3322,3325
< // .sbttl "Start the Unprivileged CALL_PAL Entry Points"
< // .sbttl "bpt- PALcode for bpt instruction"
< //+
---
> ///////////////////////////////////////////////////
> // Start the Unprivileged CALL_PAL Entry Points
> ///////////////////////////////////////////////////
>
4302a3327,3328
> // bpt - PALcode for bpt instruction
> //
4313d3338
< //-
4314a3340
> //
4343,4344d3368
< // .sbttl "bugchk- PALcode for bugchk instruction"
< //+
4345a3370,3371
> // bugchk - PALcode for bugchk instruction
> //
4356d3381
< //-
4357a3383
> //
4388,4389d3413
< // .sbttl "callsys - PALcode for callsys instruction"
< //+
4390a3415,3416
> // callsys - PALcode for callsys instruction
> //
4400d3425
< //-
4401a3427
> //
4411c3437
< //+
---
> //
4413c3439
< //-
---
> //
4443,4444d3468
< // .sbttl "imb - PALcode for imb instruction"
< //+
4445a3470,3471
> // imb - PALcode for imb instruction
> //
4452d3477
< //-
4453a3479
> //
4463c3489
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
4557,4558d3582
< // .sbttl "rdunique - PALcode for rdunique instruction"
< //+
4559a3584,3585
> // rdunique - PALcode for rdunique instruction
> //
4566d3591
< //-
4567a3593
> //
4571c3597
< ldqp r0, osfpcb_q_unique(r0) // get new value
---
> ldq_p r0, osfpcb_q_unique(r0) // get new value
4575,4576d3600
< // .sbttl "wrunique - PALcode for wrunique instruction"
< //+
4577a3602,3603
> // wrunique - PALcode for wrunique instruction
> //
4584d3609
< //-
4585a3611
> //
4590c3616
< stqp r16, osfpcb_q_unique(r12)// get new value
---
> stq_p r16, osfpcb_q_unique(r12)// get new value
4594c3620
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
4637,4638c3663,3665
< // .sbttl "gentrap - PALcode for gentrap instruction"
< //+
---
> //
> // gentrap - PALcode for gentrap instruction
> //
4650c3677
< //-
---
> //
4679c3706
< // .sbttl "CALL_PAL OPCDECs"
---
> // CALL_PAL OPCDECs
4776c3803
< // .sbttl "Continuation of MTPR_PERFMON"
---
> // Continuation of MTPR_PERFMON
4778d3804
< #if perfmon_debug == 0
4807c3833
< stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
---
> stq_p r25, ev5__bc_ctl(r14) // store to cbox ipr
4878c3904
< ldqp r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
---
> ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
4885d3910
< //orig sget_addr r12, 1<<icsr_v_pmp, r31
4890c3915
< ev5_pass2 mtpr r13, icsr // update icsr
---
> mtpr r13, icsr // update icsr
4892,4895d3916
< #if ev5_p1 != 0
< lda r12, 1(r31)
< cmovlbc r25, r12, r16 // r16<0> set if either pme=1 or sprocess=0 (sprocess in bit 0 of r25)
< #else
4897d3917
< #endif
4985c4005
< //orig get_addr r8, (1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk), r31 // build mode mask for pmctr register
---
> // build mode mask for pmctr register
4993c4013,4014
< //;the following code will only be used in pass2, but should not hurt anything if run in pass1.
---
> // the following code will only be used in pass2, but should
> // not hurt anything if run in pass1.
4999c4020
< ev5_pass2 mtpr r8, icsr // 4 bubbles to hw_rei
---
> mtpr r8, icsr // 4 bubbles to hw_rei
5003c4024,4025
< //;the following code not needed for pass2 and later, but should work anyway.
---
> // the following code not needed for pass2 and later, but
> // should work anyway.
5021c4043
< // I guess this should be a shift of 4 bits from the above control register structure .. pb
---
> // I guess this should be a shift of 4 bits from the above control register structure
5046,5047c4068
< //orig get_addr r9, 0xFFFFFFFF, r31, verify=0 // ctr2<15:0>,ctr1<15:0> mask
< LDLI(r9, (0xFFFFFFFF))
---
> LDLI(r9, (0xFFFFFFFF)) // ctr2<15:0>,ctr1<15:0> mask
5065d4085
< #else
5067c4087,4089
< // end of "real code", start of debug code
---
> //////////////////////////////////////////////////////////
> // Copy code
> //////////////////////////////////////////////////////////
5069,5178d4090
< //+
< // Debug environment:
< // (in pass2, always set icsr<pma> to ensure master counter enable is on)
< // R16 = 0 Write to on-chip performance monitor ipr
< // r17 = on-chip ipr
< // r0 = return value of read of on-chip performance monitor ipr
< // R16 = 1 Setup Cbox mux selects
< // r17 = Cbox mux selects in same position as in bc_ctl ipr.
< // r0 = return value of read of on-chip performance monitor ipr
< //
< //-
< pal_perfmon_debug:
< mfpr r8, icsr
< lda r9, 1<<icsr_v_pma(r31)
< bis r8, r9, r8
< mtpr r8, icsr
<
< mfpr r0, ev5__pmctr // read old value
< bne r16, cbox_mux_sel
<
< mtpr r17, ev5__pmctr // update pmctr ipr
< br r31, end_pm
<
< cbox_mux_sel:
< // ok, now tackle cbox mux selects
< ldah r14, 0xfff0(r31)
< zap r14, 0xE0, r14 // Get Cbox IPR base
< //orig get_bc_ctl_shadow r16 // bc_ctl returned
< mfpr r16, pt_impure
< lda r16, CNS_Q_IPR(r16)
< RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
<
< lda r8, 0x3F(r31) // build mux select mask
< sll r8, BC_CTL_V_PM_MUX_SEL, r8
<
< and r17, r8, r25 // isolate bc_ctl mux select bits
< bic r16, r8, r16 // isolate old mux select bits
< or r16, r25, r25 // create new bc_ctl
< mb // clear out cbox for future ipr write
< stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
< mb // clear out cbox for future ipr write
< //orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
< mfpr r16, pt_impure
< lda r16, CNS_Q_IPR(r16)
< SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
<
< end_pm: hw_rei
<
< #endif
<
<
< //;The following code is a workaround for a cpu bug where Istream prefetches to
< //;super-page address space in user mode may escape off-chip.
< #if spe_fix != 0
<
< ALIGN_BLOCK
< hw_rei_update_spe:
< mfpr r12, pt_misc // get previous mode
< srl r11, osfps_v_mode, r10 // isolate current mode bit
< and r10, 1, r10
< extbl r12, 7, r8 // get previous mode field
< and r8, 1, r8 // isolate previous mode bit
< cmpeq r10, r8, r8 // compare previous and current modes
< beq r8, hw_rei_update_spe_5_
< hw_rei // if same, just return
<
< hw_rei_update_spe_5_:
<
< #if fill_err_hack != 0
<
< fill_error_hack
< #endif
<
< mfpr r8, icsr // get current icsr value
< ldah r9, (2<<(icsr_v_spe-16))(r31) // get spe bit mask
< bic r8, r9, r8 // disable spe
< xor r10, 1, r9 // flip mode for new spe bit
< sll r9, icsr_v_spe+1, r9 // shift into position
< bis r8, r9, r8 // enable/disable spe
< lda r9, 1(r31) // now update our flag
< sll r9, pt_misc_v_cm, r9 // previous mode saved bit mask
< bic r12, r9, r12 // clear saved previous mode
< sll r10, pt_misc_v_cm, r9 // current mode saved bit mask
< bis r12, r9, r12 // set saved current mode
< mtpr r12, pt_misc // update pt_misc
< mtpr r8, icsr // update icsr
<
< #if osf_chm_fix != 0
<
<
< blbc r10, hw_rei_update_spe_10_ // branch if not user mode
<
< mb // ensure no outstanding fills
< lda r12, 1<<dc_mode_v_dc_ena(r31) // User mode
< mtpr r12, dc_mode // Turn on dcache
< mtpr r31, dc_flush // and flush it
< br r31, pal_ic_flush
<
< hw_rei_update_spe_10_: mfpr r9, pt_pcbb // Kernel mode
< ldqp r9, osfpcb_q_Fen(r9) // get FEN
< blbc r9, pal_ic_flush // return if FP disabled
< mb // ensure no outstanding fills
< mtpr r31, dc_mode // turn off dcache
< #endif
<
<
< br r31, pal_ic_flush // Pal restriction - must flush Icache if changing ICSR<SPE>
< #endif
<
<
5181c4093,4112
< ble r18, finished #if len <=0 we are finished
---
> #ifdef CACHE_COPY
> #ifndef CACHE_COPY_UNALIGNED
> and r16, 63, r8
> and r17, 63, r9
> bis r8, r9, r8
> bne r8, cache_copy_done
> #endif
> bic r18, 63, r8
> and r18, 63, r18
> beq r8, cache_copy_done
> cache_loop:
> ldf f17, 0(r16)
> stf f17, 0(r16)
> addq r17, 64, r17
> addq r16, 64, r16
> subq r8, 64, r8
> bne r8, cache_loop
> cache_copy_done:
> #endif
> ble r18, finished // if len <=0 we are finished