1/*
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2Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
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2 * Copyright 1993, 1994 Hewlett-Packard Development Company, L.P. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ |
24
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4Permission is hereby granted, free of charge, to any person obtaining a copy of
5this software and associated documentation files (the "Software"), to deal in
6the Software without restriction, including without limitation the rights to
7use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
8of the Software, and to permit persons to whom the Software is furnished to do
9so, subject to the following conditions:
10
11The above copyright notice and this permission notice shall be included in all
12copies or substantial portions of the Software.
13
14THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20SOFTWARE.
21*/
22
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25#ifndef FROMHUDSONOSF_INCLUDED 26#define FROMHUDSONOSF_INCLUDED 1
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25/*
26 * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h]
27 * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
28 */
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27 |
28#define __OSF_LOADED 1 29/*
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31**
32** FACILITY:
33**
34** DECchip 21164 PALcode
35**
36** MODULE:
37**
38** osf.h
39**
40** MODULE DESCRIPTION:
41**
42** OSF/1 specific definitions
43**
44** AUTHOR: ER
45**
46** CREATION DATE: 24-Nov-1993
47**
48** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $
49**
50** MODIFICATION HISTORY:
51**
52** $Log: fromHudsonOsf.h,v $
53** Revision 1.1.1.1 1997/10/30 23:27:19 verghese
54** current 10/29/97
55**
56** Revision 1.1 1995/11/18 01:46:31 boyle
57** Initial revision
58**
59** Revision 1.11 1995/04/21 02:06:30 fdh
60** Replaced C++ style comments with Standard C style comments.
61**
62** Revision 1.10 1994/09/26 14:17:47 samberg
63** Complete VICE work and EB164/SD164 breakout.
64**
65** Revision 1.9 1994/07/26 17:39:10 samberg
66** Changes for SD164.
67**
68** Revision 1.8 1994/07/08 17:03:48 samberg
69** Changes to support platform specific additions
70**
71** Revision 1.7 1994/05/20 19:23:51 ericr
72** Moved STACK_FRAME macro from osfpal.s to here
73**
74** Revision 1.6 1994/05/20 18:08:19 ericr
75** Changed line comments to C++ style comment character
76**
77** Revision 1.5 1994/01/11 18:43:33 ericr
78** Removed PAL version/revision and size constants
79**
80** Revision 1.4 1994/01/05 16:22:32 ericr
81** Added more SCB vector offsets and MCHK error code
82**
83** Revision 1.3 1994/01/03 19:35:40 ericr
84** Derive mask definitions from field constants
85**
86** Revision 1.2 1993/12/22 20:43:01 eric
87** Added mask definitions for MCES bits
88**
89** Revision 1.1 1993/12/16 21:55:05 eric
90** Initial revision
91**
92**
93**--
94*/
95
96/*
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30** Seg0 and Seg1 Virtual Address (VA) Format 31** 32** Loc Size Name Function 33** ----- ---- ---- --------------------------------- 34** <42:33> 10 SEG1 First level page table offset 35** <32:23> 10 SEG2 Second level page table offset 36** <22:13> 10 SEG3 Third level page table offset 37** <12:00> 13 OFFSET Byte within page offset 38*/ 39 40#define VA_V_SEG1 33 41#define VA_M_SEG1 (0x3FF<<VA_V_SEG1) 42#define VA_V_SEG2 23 43#define VA_M_SEG2 (0x3FF<<VA_V_SEG2) 44#define VA_V_SEG3 13 45#define VA_M_SEG3 (0x3FF<<VA_V_SEG3) 46#define VA_V_OFFSET 0 47#define VA_M_OFFSET 0x1FFF 48 49/* 50** Virtual Address Options: 8K byte page size 51*/ 52 53#define VA_S_SIZE 43 54#define VA_S_OFF 13 55#define va_s_off 13 56#define VA_S_SEG 10 57#define VA_S_PAGE_SIZE 8192 58 59/* 60** Page Table Entry (PTE) Format 61** 62** Extent Size Name Function 63** ------ ---- ---- --------------------------------- 64** <63:32> 32 PFN Page Frame Number 65** <31:16> 16 SW Reserved for software 66** <15:14> 2 RSV0 Reserved for hardware SBZ 67** <13> 1 UWE User Write Enable 68** <12> 1 KWE Kernel Write Enable 69** <11:10> 2 RSV1 Reserved for hardware SBZ 70** <9> 1 URE User Read Enable 71** <8> 1 KRE Kernel Read Enable 72** <7> 1 RSV2 Reserved for hardware SBZ 73** <6:5> 2 GH Granularity Hint 74** <4> 1 ASM Address Space Match 75** <3> 1 FOE Fault On Execute 76** <2> 1 FOW Fault On Write 77** <1> 1 FOR Fault On Read 78** <0> 1 V Valid 79*/ 80 81#define PTE_V_PFN 32 82#define PTE_M_PFN 0xFFFFFFFF00000000 83#define PTE_V_SW 16 84#define PTE_M_SW 0x00000000FFFF0000 85#define PTE_V_UWE 13 86#define PTE_M_UWE (1<<PTE_V_UWE) 87#define PTE_V_KWE 12 88#define PTE_M_KWE (1<<PTE_V_KWE) 89#define PTE_V_URE 9 90#define PTE_M_URE (1<<PTE_V_URE) 91#define PTE_V_KRE 8 92#define PTE_M_KRE (1<<PTE_V_KRE) 93#define PTE_V_GH 5 94#define PTE_M_GH (3<<PTE_V_GH) 95#define PTE_V_ASM 4 96#define PTE_M_ASM (1<<PTE_V_ASM) 97#define PTE_V_FOE 3 98#define PTE_M_FOE (1<<PTE_V_FOE) 99#define PTE_V_FOW 2 100#define PTE_M_FOW (1<<PTE_V_FOW) 101#define PTE_V_FOR 1 102#define PTE_M_FOR (1<<PTE_V_FOR) 103#define PTE_V_VALID 0 104#define PTE_M_VALID (1<<PTE_V_VALID) 105 106#define PTE_M_KSEG 0x1111 107#define PTE_M_PROT 0x3300 108#define pte_m_prot 0x3300 109 110/* 111** System Entry Instruction Fault (entIF) Constants: 112*/ 113 114#define IF_K_BPT 0x0 115#define IF_K_BUGCHK 0x1 116#define IF_K_GENTRAP 0x2 117#define IF_K_FEN 0x3 118#define IF_K_OPCDEC 0x4 119 120/* 121** System Entry Hardware Interrupt (entInt) Constants: 122*/ 123 124#define INT_K_IP 0x0 125#define INT_K_CLK 0x1 126#define INT_K_MCHK 0x2 127#define INT_K_DEV 0x3 128#define INT_K_PERF 0x4 129 130/* 131** System Entry MM Fault (entMM) Constants: 132*/ 133 134#define MM_K_TNV 0x0 135#define MM_K_ACV 0x1 136#define MM_K_FOR 0x2 137#define MM_K_FOE 0x3 138#define MM_K_FOW 0x4 139 140/* 141** Process Control Block (PCB) Offsets: 142*/ 143 144#define PCB_Q_KSP 0x0000 145#define PCB_Q_USP 0x0008 146#define PCB_Q_PTBR 0x0010 147#define PCB_L_PCC 0x0018 148#define PCB_L_ASN 0x001C 149#define PCB_Q_UNIQUE 0x0020 150#define PCB_Q_FEN 0x0028 151#define PCB_Q_RSV0 0x0030 152#define PCB_Q_RSV1 0x0038 153 154/* 155** Processor Status Register (PS) Bit Summary 156** 157** Extent Size Name Function 158** ------ ---- ---- --------------------------------- 159** <3> 1 CM Current Mode 160** <2:0> 3 IPL Interrupt Priority Level 161**/ 162 163#define PS_V_CM 3 164#define PS_M_CM (1<<PS_V_CM) 165#define PS_V_IPL 0 166#define PS_M_IPL (7<<PS_V_IPL) 167 168#define PS_K_KERN (0<<PS_V_CM) 169#define PS_K_USER (1<<PS_V_CM) 170 171#define IPL_K_ZERO 0x0 172#define IPL_K_SW0 0x1 173#define IPL_K_SW1 0x2 174#define IPL_K_DEV0 0x3 175#define IPL_K_DEV1 0x4 176#define IPL_K_CLK 0x5 177#define IPL_K_RT 0x6 178#define IPL_K_PERF 0x6 179#define IPL_K_PFAIL 0x6 180#define IPL_K_MCHK 0x7 181 182#define IPL_K_LOW 0x0 183#define IPL_K_HIGH 0x7 184 185/* 186** SCB Offset Definitions: 187*/ 188 189#define SCB_Q_FEN 0x0010 190#define SCB_Q_ACV 0x0080 191#define SCB_Q_TNV 0x0090 192#define SCB_Q_FOR 0x00A0 193#define SCB_Q_FOW 0x00B0 194#define SCB_Q_FOE 0x00C0 195#define SCB_Q_ARITH 0x0200 196#define SCB_Q_KAST 0x0240 197#define SCB_Q_EAST 0x0250 198#define SCB_Q_SAST 0x0260 199#define SCB_Q_UAST 0x0270 200#define SCB_Q_UNALIGN 0x0280 201#define SCB_Q_BPT 0x0400 202#define SCB_Q_BUGCHK 0x0410 203#define SCB_Q_OPCDEC 0x0420 204#define SCB_Q_ILLPAL 0x0430 205#define SCB_Q_TRAP 0x0440 206#define SCB_Q_CHMK 0x0480 207#define SCB_Q_CHME 0x0490 208#define SCB_Q_CHMS 0x04A0 209#define SCB_Q_CHMU 0x04B0 210#define SCB_Q_SW0 0x0500 211#define SCB_Q_SW1 0x0510 212#define SCB_Q_SW2 0x0520 213#define SCB_Q_SW3 0x0530 214#define SCB_Q_SW4 0x0540 215#define SCB_Q_SW5 0x0550 216#define SCB_Q_SW6 0x0560 217#define SCB_Q_SW7 0x0570 218#define SCB_Q_SW8 0x0580 219#define SCB_Q_SW9 0x0590 220#define SCB_Q_SW10 0x05A0 221#define SCB_Q_SW11 0x05B0 222#define SCB_Q_SW12 0x05C0 223#define SCB_Q_SW13 0x05D0 224#define SCB_Q_SW14 0x05E0 225#define SCB_Q_SW15 0x05F0 226#define SCB_Q_CLOCK 0x0600 227#define SCB_Q_INTER 0x0610 228#define SCB_Q_SYSERR 0x0620 229#define SCB_Q_PROCERR 0x0630 230#define SCB_Q_PWRFAIL 0x0640 231#define SCB_Q_PERFMON 0x0650 232#define SCB_Q_SYSMCHK 0x0660 233#define SCB_Q_PROCMCHK 0x0670 234#define SCB_Q_PASSREL 0x0680 235 236/* 237** Stack Frame (FRM) Offsets: 238** 239** There are two types of system entries for OSF/1 - those for the 240** callsys CALL_PAL function and those for exceptions and interrupts. 241** Both entry types use the same stack frame layout. The stack frame 242** contains space for the PC, the PS, the saved GP, and the saved 243** argument registers a0, a1, and a2. On entry, SP points to the 244** saved PS. 245*/ 246 247#define FRM_Q_PS 0x0000 248#define FRM_Q_PC 0x0008 249#define FRM_Q_GP 0x0010 250#define FRM_Q_A0 0x0018 251#define FRM_Q_A1 0x0020 252#define FRM_Q_A2 0x0028 253 254#define FRM_K_SIZE 48 255 256#define STACK_FRAME(tmp1,tmp2) \ 257 sll ps, 63-PS_V_CM, p7; \ 258 bge p7, 0f; \ 259 bis zero, zero, ps; \ 260 mtpr sp, ptUsp; \ 261 mfpr sp, ptKsp; \ 2620: lda sp, 0-FRM_K_SIZE(sp); \ 263 stq tmp1, FRM_Q_PS(sp); \ 264 stq tmp2, FRM_Q_PC(sp); \ 265 stq gp, FRM_Q_GP(sp); \ 266 stq a0, FRM_Q_A0(sp); \ 267 stq a1, FRM_Q_A1(sp); \ 268 stq a2, FRM_Q_A2(sp) 269 270/* 271** Halt Codes: 272*/ 273 274#define HLT_K_RESET 0x0000 275#define HLT_K_HW_HALT 0x0001 276#define HLT_K_KSP_INVAL 0x0002 277#define HLT_K_SCBB_INVAL 0x0003 278#define HLT_K_PTBR_INVAL 0x0004 279#define HLT_K_SW_HALT 0x0005 280#define HLT_K_DBL_MCHK 0x0006 281#define HLT_K_MCHK_FROM_PAL 0x0007 282 283/* 284** Machine Check Codes: 285*/ 286 287#define MCHK_K_TPERR 0x0080 288#define MCHK_K_TCPERR 0x0082 289#define MCHK_K_HERR 0x0084 290#define MCHK_K_ECC_C 0x0086 291#define MCHK_K_ECC_NC 0x0088 292#define MCHK_K_UNKNOWN 0x008A 293#define MCHK_K_CACKSOFT 0x008C 294#define MCHK_K_BUGCHECK 0x008E 295#define MCHK_K_OS_BUGCHECK 0x0090 296#define MCHK_K_DCPERR 0x0092 297#define MCHK_K_ICPERR 0x0094 298#define MCHK_K_RETRY_IRD 0x0096 299#define MCHK_K_PROC_HERR 0x0098 300 301/* 302** System Machine Check Codes: 303*/ 304 305#define MCHK_K_READ_NXM 0x0200 306#define MCHK_K_SYS_HERR 0x0202 307 308/* 309** Machine Check Error Status Summary (MCES) Register Format 310** 311** Extent Size Name Function 312** ------ ---- ---- --------------------------------- 313** <0> 1 MIP Machine check in progress 314** <1> 1 SCE System correctable error in progress 315** <2> 1 PCE Processor correctable error in progress 316** <3> 1 DPC Disable PCE error reporting 317** <4> 1 DSC Disable SCE error reporting 318*/ 319 320#define MCES_V_MIP 0 321#define MCES_M_MIP (1<<MCES_V_MIP) 322#define MCES_V_SCE 1 323#define MCES_M_SCE (1<<MCES_V_SCE) 324#define MCES_V_PCE 2 325#define MCES_M_PCE (1<<MCES_V_PCE) 326#define MCES_V_DPC 3 327#define MCES_M_DPC (1<<MCES_V_DPC) 328#define MCES_V_DSC 4 329#define MCES_M_DSC (1<<MCES_V_DSC) 330 331#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \ 332 | MCES_M_DSC) 333 334/* 335** Who-Am-I (WHAMI) Register Format 336** 337** Extent Size Name Function 338** ------ ---- ---- --------------------------------- 339** <7:0> 8 ID Who-Am-I identifier 340** <15:8> 1 SWAP Swap PALcode flag - character 'S' 341*/ 342 343#define WHAMI_V_SWAP 8 344#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP) 345#define WHAMI_V_ID 0 346#define WHAMI_M_ID 0xFF 347 348#define WHAMI_K_SWAP 0x53 /* Character 'S' */ 349 350/* 351** Conventional Register Usage Definitions 352** 353** Assembler temporary `at' is `AT' so it doesn't conflict with the 354** `.set at' assembler directive. 355*/ 356 357#define v0 $0 /* Function Return Value Register */ 358#define t0 $1 /* Scratch (Temporary) Registers ... */ 359#define t1 $2 360#define t2 $3 361#define t3 $4 362#define t4 $5 363#define t5 $6 364#define t6 $7 365#define t7 $8 366#define s0 $9 /* Saved (Non-Volatile) Registers ... */ 367#define s1 $10 368#define s2 $11 369#define s3 $12 370#define s4 $13 371#define s5 $14 372#define fp $15 /* Frame Pointer Register, Or S6 */ 373#define s6 $15 374#define a0 $16 /* Argument Registers ... */ 375#define a1 $17 376#define a2 $18 377#define a3 $19 378#define a4 $20 379#define a5 $21 380#define t8 $22 /* Scratch (Temporary) Registers ... */ 381#define t9 $23 382#define t10 $24 383#define t11 $25 384#define ra $26 /* Return Address Register */ 385#define pv $27 /* Procedure Value Register, Or T12 */ 386#define t12 $27 387#define AT $28 /* Assembler Temporary (Volatile) Register */ 388#define gp $29 /* Global Pointer Register */ 389#define sp $30 /* Stack Pointer Register */ 390#define zero $31 /* Zero Register */ 391 392/* 393** OSF/1 Unprivileged CALL_PAL Entry Offsets: 394** 395** Entry Name Offset (Hex) 396** 397** bpt 0080 398** bugchk 0081 399** callsys 0083 400** imb 0086 401** rdunique 009E 402** wrunique 009F 403** gentrap 00AA 404** dbgstop 00AD 405*/ 406 407#define UNPRIV 0x80 408#define PAL_BPT_ENTRY 0x80 409#define PAL_BUGCHK_ENTRY 0x81 410#define PAL_CALLSYS_ENTRY 0x83 411#define PAL_IMB_ENTRY 0x86 412#define PAL_RDUNIQUE_ENTRY 0x9E 413#define PAL_WRUNIQUE_ENTRY 0x9F 414#define PAL_GENTRAP_ENTRY 0xAA 415 416#if defined(KDEBUG) 417#define PAL_DBGSTOP_ENTRY 0xAD 418/* #define NUM_UNPRIV_CALL_PALS 10 */ 419#else 420/* #define NUM_UNPRIV_CALL_PALS 9 */ 421#endif /* KDEBUG */ 422 423/* 424** OSF/1 Privileged CALL_PAL Entry Offsets: 425** 426** Entry Name Offset (Hex) 427** 428** halt 0000 429** cflush 0001 430** draina 0002 431** cserve 0009 432** swppal 000A 433** rdmces 0010 434** wrmces 0011 435** wrfen 002B 436** wrvptptr 002D 437** swpctx 0030 438** wrval 0031 439** rdval 0032 440** tbi 0033 441** wrent 0034 442** swpipl 0035 443** rdps 0036 444** wrkgp 0037 445** wrusp 0038 446** rdusp 003A 447** whami 003C 448** retsys 003D 449** rti 003F 450*/ 451 452#define PAL_HALT_ENTRY 0x0000 453#define PAL_CFLUSH_ENTRY 0x0001 454#define PAL_DRAINA_ENTRY 0x0002 455#define PAL_CSERVE_ENTRY 0x0009 456#define PAL_SWPPAL_ENTRY 0x000A 457#define PAL_WRIPIR_ENTRY 0x000D 458#define PAL_RDMCES_ENTRY 0x0010 459#define PAL_WRMCES_ENTRY 0x0011 460#define PAL_WRFEN_ENTRY 0x002B 461#define PAL_WRVPTPTR_ENTRY 0x002D 462#define PAL_SWPCTX_ENTRY 0x0030 463#define PAL_WRVAL_ENTRY 0x0031 464#define PAL_RDVAL_ENTRY 0x0032 465#define PAL_TBI_ENTRY 0x0033 466#define PAL_WRENT_ENTRY 0x0034 467#define PAL_SWPIPL_ENTRY 0x0035 468#define PAL_RDPS_ENTRY 0x0036 469#define PAL_WRKGP_ENTRY 0x0037 470#define PAL_WRUSP_ENTRY 0x0038 471#define PAL_RDUSP_ENTRY 0x003A 472#define PAL_WHAMI_ENTRY 0x003C 473#define PAL_RETSYS_ENTRY 0x003D 474#define PAL_RTI_ENTRY 0x003F 475 476#define NUM_PRIV_CALL_PALS 23 477 478#endif 479
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