1#ifndef FROMHUDSONOSF_INCLUDED
2#define FROMHUDSONOSF_INCLUDED 1
3/*
4 * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h]
5 * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
6 */
7#define __OSF_LOADED 1
8/*
9*****************************************************************************
10** *
11** Copyright � 1993, 1994 *
12** by Digital Equipment Corporation, Maynard, Massachusetts. *
13** *
14** All Rights Reserved *
15** *
16** Permission is hereby granted to use, copy, modify and distribute *
17** this software and its documentation, in both source code and *
18** object code form, and without fee, for the purpose of distribution *
19** of this software or modifications of this software within products *
20** incorporating an integrated circuit implementing Digital's AXP *
21** architecture, regardless of the source of such integrated circuit, *
22** provided that the above copyright notice and this permission notice *
23** appear in all copies, and that the name of Digital Equipment *
24** Corporation not be used in advertising or publicity pertaining to *
25** distribution of the document or software without specific, written *
26** prior permission. *
27** *
28** Digital Equipment Corporation disclaims all warranties and/or *
29** guarantees with regard to this software, including all implied *
30** warranties of fitness for a particular purpose and merchantability, *
31** and makes no representations regarding the use of, or the results *
32** of the use of, the software and documentation in terms of correctness, *
33** accuracy, reliability, currentness or otherwise; and you rely on *
34** the software, documentation and results solely at your own risk. *
35** *
36** AXP is a trademark of Digital Equipment Corporation. *
37** *
38*****************************************************************************
39**
40** FACILITY:
41**
42** DECchip 21164 PALcode
43**
44** MODULE:
45**
46** osf.h
47**
48** MODULE DESCRIPTION:
49**
50** OSF/1 specific definitions
51**
52** AUTHOR: ER
53**
54** CREATION DATE: 24-Nov-1993
55**
56** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $
57**
58** MODIFICATION HISTORY:
59**
60** $Log: fromHudsonOsf.h,v $
61** Revision 1.1.1.1 1997/10/30 23:27:19 verghese
62** current 10/29/97
63**
64** Revision 1.1 1995/11/18 01:46:31 boyle
65** Initial revision
66**
67** Revision 1.11 1995/04/21 02:06:30 fdh
68** Replaced C++ style comments with Standard C style comments.
69**
70** Revision 1.10 1994/09/26 14:17:47 samberg
71** Complete VICE work and EB164/SD164 breakout.
72**
73** Revision 1.9 1994/07/26 17:39:10 samberg
74** Changes for SD164.
75**
76** Revision 1.8 1994/07/08 17:03:48 samberg
77** Changes to support platform specific additions
78**
79** Revision 1.7 1994/05/20 19:23:51 ericr
80** Moved STACK_FRAME macro from osfpal.s to here
81**
82** Revision 1.6 1994/05/20 18:08:19 ericr
83** Changed line comments to C++ style comment character
84**
85** Revision 1.5 1994/01/11 18:43:33 ericr
86** Removed PAL version/revision and size constants
87**
88** Revision 1.4 1994/01/05 16:22:32 ericr
89** Added more SCB vector offsets and MCHK error code
90**
91** Revision 1.3 1994/01/03 19:35:40 ericr
92** Derive mask definitions from field constants
93**
94** Revision 1.2 1993/12/22 20:43:01 eric
95** Added mask definitions for MCES bits
96**
97** Revision 1.1 1993/12/16 21:55:05 eric
98** Initial revision
99**
100**
101**--
102*/
103
104/*
105** Seg0 and Seg1 Virtual Address (VA) Format
106**
107** Loc Size Name Function
108** ----- ---- ---- ---------------------------------
109** <42:33> 10 SEG1 First level page table offset
110** <32:23> 10 SEG2 Second level page table offset
111** <22:13> 10 SEG3 Third level page table offset
112** <12:00> 13 OFFSET Byte within page offset
113*/
114
115#define VA_V_SEG1 33
116#define VA_M_SEG1 (0x3FF<<VA_V_SEG1)
117#define VA_V_SEG2 23
118#define VA_M_SEG2 (0x3FF<<VA_V_SEG2)
119#define VA_V_SEG3 13
120#define VA_M_SEG3 (0x3FF<<VA_V_SEG3)
121#define VA_V_OFFSET 0
122#define VA_M_OFFSET 0x1FFF
123
124/*
125** Virtual Address Options: 8K byte page size
126*/
127
128#define VA_S_SIZE 43
129#define VA_S_OFF 13
130#define va_s_off 13
131#define VA_S_SEG 10
132#define VA_S_PAGE_SIZE 8192
133
134/*
135** Page Table Entry (PTE) Format
136**
137** Extent Size Name Function
138** ------ ---- ---- ---------------------------------
139** <63:32> 32 PFN Page Frame Number
140** <31:16> 16 SW Reserved for software
141** <15:14> 2 RSV0 Reserved for hardware SBZ
142** <13> 1 UWE User Write Enable
143** <12> 1 KWE Kernel Write Enable
144** <11:10> 2 RSV1 Reserved for hardware SBZ
145** <9> 1 URE User Read Enable
146** <8> 1 KRE Kernel Read Enable
147** <7> 1 RSV2 Reserved for hardware SBZ
148** <6:5> 2 GH Granularity Hint
149** <4> 1 ASM Address Space Match
150** <3> 1 FOE Fault On Execute
151** <2> 1 FOW Fault On Write
152** <1> 1 FOR Fault On Read
153** <0> 1 V Valid
154*/
155
156#define PTE_V_PFN 32
157#define PTE_M_PFN 0xFFFFFFFF00000000
158#define PTE_V_SW 16
159#define PTE_M_SW 0x00000000FFFF0000
160#define PTE_V_UWE 13
161#define PTE_M_UWE (1<<PTE_V_UWE)
162#define PTE_V_KWE 12
163#define PTE_M_KWE (1<<PTE_V_KWE)
164#define PTE_V_URE 9
165#define PTE_M_URE (1<<PTE_V_URE)
166#define PTE_V_KRE 8
167#define PTE_M_KRE (1<<PTE_V_KRE)
168#define PTE_V_GH 5
169#define PTE_M_GH (3<<PTE_V_GH)
170#define PTE_V_ASM 4
171#define PTE_M_ASM (1<<PTE_V_ASM)
172#define PTE_V_FOE 3
173#define PTE_M_FOE (1<<PTE_V_FOE)
174#define PTE_V_FOW 2
175#define PTE_M_FOW (1<<PTE_V_FOW)
176#define PTE_V_FOR 1
177#define PTE_M_FOR (1<<PTE_V_FOR)
178#define PTE_V_VALID 0
179#define PTE_M_VALID (1<<PTE_V_VALID)
180
181#define PTE_M_KSEG 0x1111
182#define PTE_M_PROT 0x3300
183#define pte_m_prot 0x3300
184
185/*
186** System Entry Instruction Fault (entIF) Constants:
187*/
188
189#define IF_K_BPT 0x0
190#define IF_K_BUGCHK 0x1
191#define IF_K_GENTRAP 0x2
192#define IF_K_FEN 0x3
193#define IF_K_OPCDEC 0x4
194
195/*
196** System Entry Hardware Interrupt (entInt) Constants:
197*/
198
199#define INT_K_IP 0x0
200#define INT_K_CLK 0x1
201#define INT_K_MCHK 0x2
202#define INT_K_DEV 0x3
203#define INT_K_PERF 0x4
204
205/*
206** System Entry MM Fault (entMM) Constants:
207*/
208
209#define MM_K_TNV 0x0
210#define MM_K_ACV 0x1
211#define MM_K_FOR 0x2
212#define MM_K_FOE 0x3
213#define MM_K_FOW 0x4
214
215/*
216** Process Control Block (PCB) Offsets:
217*/
218
219#define PCB_Q_KSP 0x0000
220#define PCB_Q_USP 0x0008
221#define PCB_Q_PTBR 0x0010
222#define PCB_L_PCC 0x0018
223#define PCB_L_ASN 0x001C
224#define PCB_Q_UNIQUE 0x0020
225#define PCB_Q_FEN 0x0028
226#define PCB_Q_RSV0 0x0030
227#define PCB_Q_RSV1 0x0038
228
229/*
230** Processor Status Register (PS) Bit Summary
231**
232** Extent Size Name Function
233** ------ ---- ---- ---------------------------------
234** <3> 1 CM Current Mode
235** <2:0> 3 IPL Interrupt Priority Level
236**/
237
238#define PS_V_CM 3
239#define PS_M_CM (1<<PS_V_CM)
240#define PS_V_IPL 0
241#define PS_M_IPL (7<<PS_V_IPL)
242
243#define PS_K_KERN (0<<PS_V_CM)
244#define PS_K_USER (1<<PS_V_CM)
245
246#define IPL_K_ZERO 0x0
247#define IPL_K_SW0 0x1
248#define IPL_K_SW1 0x2
249#define IPL_K_DEV0 0x3
250#define IPL_K_DEV1 0x4
251#define IPL_K_CLK 0x5
252#define IPL_K_RT 0x6
253#define IPL_K_PERF 0x6
254#define IPL_K_PFAIL 0x6
255#define IPL_K_MCHK 0x7
256
257#define IPL_K_LOW 0x0
258#define IPL_K_HIGH 0x7
259
260/*
261** SCB Offset Definitions:
262*/
263
264#define SCB_Q_FEN 0x0010
265#define SCB_Q_ACV 0x0080
266#define SCB_Q_TNV 0x0090
267#define SCB_Q_FOR 0x00A0
268#define SCB_Q_FOW 0x00B0
269#define SCB_Q_FOE 0x00C0
270#define SCB_Q_ARITH 0x0200
271#define SCB_Q_KAST 0x0240
272#define SCB_Q_EAST 0x0250
273#define SCB_Q_SAST 0x0260
274#define SCB_Q_UAST 0x0270
275#define SCB_Q_UNALIGN 0x0280
276#define SCB_Q_BPT 0x0400
277#define SCB_Q_BUGCHK 0x0410
278#define SCB_Q_OPCDEC 0x0420
279#define SCB_Q_ILLPAL 0x0430
280#define SCB_Q_TRAP 0x0440
281#define SCB_Q_CHMK 0x0480
282#define SCB_Q_CHME 0x0490
283#define SCB_Q_CHMS 0x04A0
284#define SCB_Q_CHMU 0x04B0
285#define SCB_Q_SW0 0x0500
286#define SCB_Q_SW1 0x0510
287#define SCB_Q_SW2 0x0520
288#define SCB_Q_SW3 0x0530
289#define SCB_Q_SW4 0x0540
290#define SCB_Q_SW5 0x0550
291#define SCB_Q_SW6 0x0560
292#define SCB_Q_SW7 0x0570
293#define SCB_Q_SW8 0x0580
294#define SCB_Q_SW9 0x0590
295#define SCB_Q_SW10 0x05A0
296#define SCB_Q_SW11 0x05B0
297#define SCB_Q_SW12 0x05C0
298#define SCB_Q_SW13 0x05D0
299#define SCB_Q_SW14 0x05E0
300#define SCB_Q_SW15 0x05F0
301#define SCB_Q_CLOCK 0x0600
302#define SCB_Q_INTER 0x0610
303#define SCB_Q_SYSERR 0x0620
304#define SCB_Q_PROCERR 0x0630
305#define SCB_Q_PWRFAIL 0x0640
306#define SCB_Q_PERFMON 0x0650
307#define SCB_Q_SYSMCHK 0x0660
308#define SCB_Q_PROCMCHK 0x0670
309#define SCB_Q_PASSREL 0x0680
310
311/*
312** Stack Frame (FRM) Offsets:
313**
314** There are two types of system entries for OSF/1 - those for the
315** callsys CALL_PAL function and those for exceptions and interrupts.
316** Both entry types use the same stack frame layout. The stack frame
317** contains space for the PC, the PS, the saved GP, and the saved
318** argument registers a0, a1, and a2. On entry, SP points to the
319** saved PS.
320*/
321
322#define FRM_Q_PS 0x0000
323#define FRM_Q_PC 0x0008
324#define FRM_Q_GP 0x0010
325#define FRM_Q_A0 0x0018
326#define FRM_Q_A1 0x0020
327#define FRM_Q_A2 0x0028
328
329#define FRM_K_SIZE 48
330
331#define STACK_FRAME(tmp1,tmp2) \
332 sll ps, 63-PS_V_CM, p7; \
333 bge p7, 0f; \
334 bis zero, zero, ps; \
335 mtpr sp, ptUsp; \
336 mfpr sp, ptKsp; \
3370: lda sp, 0-FRM_K_SIZE(sp); \
338 stq tmp1, FRM_Q_PS(sp); \
339 stq tmp2, FRM_Q_PC(sp); \
340 stq gp, FRM_Q_GP(sp); \
341 stq a0, FRM_Q_A0(sp); \
342 stq a1, FRM_Q_A1(sp); \
343 stq a2, FRM_Q_A2(sp)
344
345/*
346** Halt Codes:
347*/
348
349#define HLT_K_RESET 0x0000
350#define HLT_K_HW_HALT 0x0001
351#define HLT_K_KSP_INVAL 0x0002
352#define HLT_K_SCBB_INVAL 0x0003
353#define HLT_K_PTBR_INVAL 0x0004
354#define HLT_K_SW_HALT 0x0005
355#define HLT_K_DBL_MCHK 0x0006
356#define HLT_K_MCHK_FROM_PAL 0x0007
357
358/*
359** Machine Check Codes:
360*/
361
362#define MCHK_K_TPERR 0x0080
363#define MCHK_K_TCPERR 0x0082
364#define MCHK_K_HERR 0x0084
365#define MCHK_K_ECC_C 0x0086
366#define MCHK_K_ECC_NC 0x0088
367#define MCHK_K_UNKNOWN 0x008A
368#define MCHK_K_CACKSOFT 0x008C
369#define MCHK_K_BUGCHECK 0x008E
370#define MCHK_K_OS_BUGCHECK 0x0090
371#define MCHK_K_DCPERR 0x0092
372#define MCHK_K_ICPERR 0x0094
373#define MCHK_K_RETRY_IRD 0x0096
374#define MCHK_K_PROC_HERR 0x0098
375
376/*
377** System Machine Check Codes:
378*/
379
380#define MCHK_K_READ_NXM 0x0200
381#define MCHK_K_SYS_HERR 0x0202
382
383/*
384** Machine Check Error Status Summary (MCES) Register Format
385**
386** Extent Size Name Function
387** ------ ---- ---- ---------------------------------
388** <0> 1 MIP Machine check in progress
389** <1> 1 SCE System correctable error in progress
390** <2> 1 PCE Processor correctable error in progress
391** <3> 1 DPC Disable PCE error reporting
392** <4> 1 DSC Disable SCE error reporting
393*/
394
395#define MCES_V_MIP 0
396#define MCES_M_MIP (1<<MCES_V_MIP)
397#define MCES_V_SCE 1
398#define MCES_M_SCE (1<<MCES_V_SCE)
399#define MCES_V_PCE 2
400#define MCES_M_PCE (1<<MCES_V_PCE)
401#define MCES_V_DPC 3
402#define MCES_M_DPC (1<<MCES_V_DPC)
403#define MCES_V_DSC 4
404#define MCES_M_DSC (1<<MCES_V_DSC)
405
406#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
407 | MCES_M_DSC)
408
409/*
410** Who-Am-I (WHAMI) Register Format
411**
412** Extent Size Name Function
413** ------ ---- ---- ---------------------------------
414** <7:0> 8 ID Who-Am-I identifier
415** <15:8> 1 SWAP Swap PALcode flag - character 'S'
416*/
417
418#define WHAMI_V_SWAP 8
419#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP)
420#define WHAMI_V_ID 0
421#define WHAMI_M_ID 0xFF
422
423#define WHAMI_K_SWAP 0x53 /* Character 'S' */
424
425/*
426** Conventional Register Usage Definitions
427**
428** Assembler temporary `at' is `AT' so it doesn't conflict with the
429** `.set at' assembler directive.
430*/
431
432#define v0 $0 /* Function Return Value Register */
433#define t0 $1 /* Scratch (Temporary) Registers ... */
434#define t1 $2
435#define t2 $3
436#define t3 $4
437#define t4 $5
438#define t5 $6
439#define t6 $7
440#define t7 $8
441#define s0 $9 /* Saved (Non-Volatile) Registers ... */
442#define s1 $10
443#define s2 $11
444#define s3 $12
445#define s4 $13
446#define s5 $14
447#define fp $15 /* Frame Pointer Register, Or S6 */
448#define s6 $15
449#define a0 $16 /* Argument Registers ... */
450#define a1 $17
451#define a2 $18
452#define a3 $19
453#define a4 $20
454#define a5 $21
455#define t8 $22 /* Scratch (Temporary) Registers ... */
456#define t9 $23
457#define t10 $24
458#define t11 $25
459#define ra $26 /* Return Address Register */
460#define pv $27 /* Procedure Value Register, Or T12 */
461#define t12 $27
462#define AT $28 /* Assembler Temporary (Volatile) Register */
463#define gp $29 /* Global Pointer Register */
464#define sp $30 /* Stack Pointer Register */
465#define zero $31 /* Zero Register */
466
467/*
468** OSF/1 Unprivileged CALL_PAL Entry Offsets:
469**
470** Entry Name Offset (Hex)
471**
472** bpt 0080
473** bugchk 0081
474** callsys 0083
475** imb 0086
476** rdunique 009E
477** wrunique 009F
478** gentrap 00AA
479** dbgstop 00AD
480*/
481
482#define UNPRIV 0x80
483#define PAL_BPT_ENTRY 0x80
484#define PAL_BUGCHK_ENTRY 0x81
485#define PAL_CALLSYS_ENTRY 0x83
486#define PAL_IMB_ENTRY 0x86
487#define PAL_RDUNIQUE_ENTRY 0x9E
488#define PAL_WRUNIQUE_ENTRY 0x9F
489#define PAL_GENTRAP_ENTRY 0xAA
490
491#if defined(KDEBUG)
492#define PAL_DBGSTOP_ENTRY 0xAD
493/* #define NUM_UNPRIV_CALL_PALS 10 */
494#else
495/* #define NUM_UNPRIV_CALL_PALS 9 */
496#endif /* KDEBUG */
497
498/*
499** OSF/1 Privileged CALL_PAL Entry Offsets:
500**
501** Entry Name Offset (Hex)
502**
503** halt 0000
504** cflush 0001
505** draina 0002
506** cserve 0009
507** swppal 000A
508** rdmces 0010
509** wrmces 0011
510** wrfen 002B
511** wrvptptr 002D
512** swpctx 0030
513** wrval 0031
514** rdval 0032
515** tbi 0033
516** wrent 0034
517** swpipl 0035
518** rdps 0036
519** wrkgp 0037
520** wrusp 0038
521** rdusp 003A
522** whami 003C
523** retsys 003D
524** rti 003F
525*/
526
527#define PAL_HALT_ENTRY 0x0000
528#define PAL_CFLUSH_ENTRY 0x0001
529#define PAL_DRAINA_ENTRY 0x0002
530#define PAL_CSERVE_ENTRY 0x0009
531#define PAL_SWPPAL_ENTRY 0x000A
532#define PAL_WRIPIR_ENTRY 0x000D
533#define PAL_RDMCES_ENTRY 0x0010
534#define PAL_WRMCES_ENTRY 0x0011
535#define PAL_WRFEN_ENTRY 0x002B
536#define PAL_WRVPTPTR_ENTRY 0x002D
537#define PAL_SWPCTX_ENTRY 0x0030
538#define PAL_WRVAL_ENTRY 0x0031
539#define PAL_RDVAL_ENTRY 0x0032
540#define PAL_TBI_ENTRY 0x0033
541#define PAL_WRENT_ENTRY 0x0034
542#define PAL_SWPIPL_ENTRY 0x0035
543#define PAL_RDPS_ENTRY 0x0036
544#define PAL_WRKGP_ENTRY 0x0037
545#define PAL_WRUSP_ENTRY 0x0038
546#define PAL_RDUSP_ENTRY 0x003A
547#define PAL_WHAMI_ENTRY 0x003C
548#define PAL_RETSYS_ENTRY 0x003D
549#define PAL_RTI_ENTRY 0x003F
550
551#define NUM_PRIV_CALL_PALS 23
552
553#endif
554
2#define FROMHUDSONOSF_INCLUDED 1
3/*
4 * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h]
5 * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
6 */
7#define __OSF_LOADED 1
8/*
9*****************************************************************************
10** *
11** Copyright � 1993, 1994 *
12** by Digital Equipment Corporation, Maynard, Massachusetts. *
13** *
14** All Rights Reserved *
15** *
16** Permission is hereby granted to use, copy, modify and distribute *
17** this software and its documentation, in both source code and *
18** object code form, and without fee, for the purpose of distribution *
19** of this software or modifications of this software within products *
20** incorporating an integrated circuit implementing Digital's AXP *
21** architecture, regardless of the source of such integrated circuit, *
22** provided that the above copyright notice and this permission notice *
23** appear in all copies, and that the name of Digital Equipment *
24** Corporation not be used in advertising or publicity pertaining to *
25** distribution of the document or software without specific, written *
26** prior permission. *
27** *
28** Digital Equipment Corporation disclaims all warranties and/or *
29** guarantees with regard to this software, including all implied *
30** warranties of fitness for a particular purpose and merchantability, *
31** and makes no representations regarding the use of, or the results *
32** of the use of, the software and documentation in terms of correctness, *
33** accuracy, reliability, currentness or otherwise; and you rely on *
34** the software, documentation and results solely at your own risk. *
35** *
36** AXP is a trademark of Digital Equipment Corporation. *
37** *
38*****************************************************************************
39**
40** FACILITY:
41**
42** DECchip 21164 PALcode
43**
44** MODULE:
45**
46** osf.h
47**
48** MODULE DESCRIPTION:
49**
50** OSF/1 specific definitions
51**
52** AUTHOR: ER
53**
54** CREATION DATE: 24-Nov-1993
55**
56** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $
57**
58** MODIFICATION HISTORY:
59**
60** $Log: fromHudsonOsf.h,v $
61** Revision 1.1.1.1 1997/10/30 23:27:19 verghese
62** current 10/29/97
63**
64** Revision 1.1 1995/11/18 01:46:31 boyle
65** Initial revision
66**
67** Revision 1.11 1995/04/21 02:06:30 fdh
68** Replaced C++ style comments with Standard C style comments.
69**
70** Revision 1.10 1994/09/26 14:17:47 samberg
71** Complete VICE work and EB164/SD164 breakout.
72**
73** Revision 1.9 1994/07/26 17:39:10 samberg
74** Changes for SD164.
75**
76** Revision 1.8 1994/07/08 17:03:48 samberg
77** Changes to support platform specific additions
78**
79** Revision 1.7 1994/05/20 19:23:51 ericr
80** Moved STACK_FRAME macro from osfpal.s to here
81**
82** Revision 1.6 1994/05/20 18:08:19 ericr
83** Changed line comments to C++ style comment character
84**
85** Revision 1.5 1994/01/11 18:43:33 ericr
86** Removed PAL version/revision and size constants
87**
88** Revision 1.4 1994/01/05 16:22:32 ericr
89** Added more SCB vector offsets and MCHK error code
90**
91** Revision 1.3 1994/01/03 19:35:40 ericr
92** Derive mask definitions from field constants
93**
94** Revision 1.2 1993/12/22 20:43:01 eric
95** Added mask definitions for MCES bits
96**
97** Revision 1.1 1993/12/16 21:55:05 eric
98** Initial revision
99**
100**
101**--
102*/
103
104/*
105** Seg0 and Seg1 Virtual Address (VA) Format
106**
107** Loc Size Name Function
108** ----- ---- ---- ---------------------------------
109** <42:33> 10 SEG1 First level page table offset
110** <32:23> 10 SEG2 Second level page table offset
111** <22:13> 10 SEG3 Third level page table offset
112** <12:00> 13 OFFSET Byte within page offset
113*/
114
115#define VA_V_SEG1 33
116#define VA_M_SEG1 (0x3FF<<VA_V_SEG1)
117#define VA_V_SEG2 23
118#define VA_M_SEG2 (0x3FF<<VA_V_SEG2)
119#define VA_V_SEG3 13
120#define VA_M_SEG3 (0x3FF<<VA_V_SEG3)
121#define VA_V_OFFSET 0
122#define VA_M_OFFSET 0x1FFF
123
124/*
125** Virtual Address Options: 8K byte page size
126*/
127
128#define VA_S_SIZE 43
129#define VA_S_OFF 13
130#define va_s_off 13
131#define VA_S_SEG 10
132#define VA_S_PAGE_SIZE 8192
133
134/*
135** Page Table Entry (PTE) Format
136**
137** Extent Size Name Function
138** ------ ---- ---- ---------------------------------
139** <63:32> 32 PFN Page Frame Number
140** <31:16> 16 SW Reserved for software
141** <15:14> 2 RSV0 Reserved for hardware SBZ
142** <13> 1 UWE User Write Enable
143** <12> 1 KWE Kernel Write Enable
144** <11:10> 2 RSV1 Reserved for hardware SBZ
145** <9> 1 URE User Read Enable
146** <8> 1 KRE Kernel Read Enable
147** <7> 1 RSV2 Reserved for hardware SBZ
148** <6:5> 2 GH Granularity Hint
149** <4> 1 ASM Address Space Match
150** <3> 1 FOE Fault On Execute
151** <2> 1 FOW Fault On Write
152** <1> 1 FOR Fault On Read
153** <0> 1 V Valid
154*/
155
156#define PTE_V_PFN 32
157#define PTE_M_PFN 0xFFFFFFFF00000000
158#define PTE_V_SW 16
159#define PTE_M_SW 0x00000000FFFF0000
160#define PTE_V_UWE 13
161#define PTE_M_UWE (1<<PTE_V_UWE)
162#define PTE_V_KWE 12
163#define PTE_M_KWE (1<<PTE_V_KWE)
164#define PTE_V_URE 9
165#define PTE_M_URE (1<<PTE_V_URE)
166#define PTE_V_KRE 8
167#define PTE_M_KRE (1<<PTE_V_KRE)
168#define PTE_V_GH 5
169#define PTE_M_GH (3<<PTE_V_GH)
170#define PTE_V_ASM 4
171#define PTE_M_ASM (1<<PTE_V_ASM)
172#define PTE_V_FOE 3
173#define PTE_M_FOE (1<<PTE_V_FOE)
174#define PTE_V_FOW 2
175#define PTE_M_FOW (1<<PTE_V_FOW)
176#define PTE_V_FOR 1
177#define PTE_M_FOR (1<<PTE_V_FOR)
178#define PTE_V_VALID 0
179#define PTE_M_VALID (1<<PTE_V_VALID)
180
181#define PTE_M_KSEG 0x1111
182#define PTE_M_PROT 0x3300
183#define pte_m_prot 0x3300
184
185/*
186** System Entry Instruction Fault (entIF) Constants:
187*/
188
189#define IF_K_BPT 0x0
190#define IF_K_BUGCHK 0x1
191#define IF_K_GENTRAP 0x2
192#define IF_K_FEN 0x3
193#define IF_K_OPCDEC 0x4
194
195/*
196** System Entry Hardware Interrupt (entInt) Constants:
197*/
198
199#define INT_K_IP 0x0
200#define INT_K_CLK 0x1
201#define INT_K_MCHK 0x2
202#define INT_K_DEV 0x3
203#define INT_K_PERF 0x4
204
205/*
206** System Entry MM Fault (entMM) Constants:
207*/
208
209#define MM_K_TNV 0x0
210#define MM_K_ACV 0x1
211#define MM_K_FOR 0x2
212#define MM_K_FOE 0x3
213#define MM_K_FOW 0x4
214
215/*
216** Process Control Block (PCB) Offsets:
217*/
218
219#define PCB_Q_KSP 0x0000
220#define PCB_Q_USP 0x0008
221#define PCB_Q_PTBR 0x0010
222#define PCB_L_PCC 0x0018
223#define PCB_L_ASN 0x001C
224#define PCB_Q_UNIQUE 0x0020
225#define PCB_Q_FEN 0x0028
226#define PCB_Q_RSV0 0x0030
227#define PCB_Q_RSV1 0x0038
228
229/*
230** Processor Status Register (PS) Bit Summary
231**
232** Extent Size Name Function
233** ------ ---- ---- ---------------------------------
234** <3> 1 CM Current Mode
235** <2:0> 3 IPL Interrupt Priority Level
236**/
237
238#define PS_V_CM 3
239#define PS_M_CM (1<<PS_V_CM)
240#define PS_V_IPL 0
241#define PS_M_IPL (7<<PS_V_IPL)
242
243#define PS_K_KERN (0<<PS_V_CM)
244#define PS_K_USER (1<<PS_V_CM)
245
246#define IPL_K_ZERO 0x0
247#define IPL_K_SW0 0x1
248#define IPL_K_SW1 0x2
249#define IPL_K_DEV0 0x3
250#define IPL_K_DEV1 0x4
251#define IPL_K_CLK 0x5
252#define IPL_K_RT 0x6
253#define IPL_K_PERF 0x6
254#define IPL_K_PFAIL 0x6
255#define IPL_K_MCHK 0x7
256
257#define IPL_K_LOW 0x0
258#define IPL_K_HIGH 0x7
259
260/*
261** SCB Offset Definitions:
262*/
263
264#define SCB_Q_FEN 0x0010
265#define SCB_Q_ACV 0x0080
266#define SCB_Q_TNV 0x0090
267#define SCB_Q_FOR 0x00A0
268#define SCB_Q_FOW 0x00B0
269#define SCB_Q_FOE 0x00C0
270#define SCB_Q_ARITH 0x0200
271#define SCB_Q_KAST 0x0240
272#define SCB_Q_EAST 0x0250
273#define SCB_Q_SAST 0x0260
274#define SCB_Q_UAST 0x0270
275#define SCB_Q_UNALIGN 0x0280
276#define SCB_Q_BPT 0x0400
277#define SCB_Q_BUGCHK 0x0410
278#define SCB_Q_OPCDEC 0x0420
279#define SCB_Q_ILLPAL 0x0430
280#define SCB_Q_TRAP 0x0440
281#define SCB_Q_CHMK 0x0480
282#define SCB_Q_CHME 0x0490
283#define SCB_Q_CHMS 0x04A0
284#define SCB_Q_CHMU 0x04B0
285#define SCB_Q_SW0 0x0500
286#define SCB_Q_SW1 0x0510
287#define SCB_Q_SW2 0x0520
288#define SCB_Q_SW3 0x0530
289#define SCB_Q_SW4 0x0540
290#define SCB_Q_SW5 0x0550
291#define SCB_Q_SW6 0x0560
292#define SCB_Q_SW7 0x0570
293#define SCB_Q_SW8 0x0580
294#define SCB_Q_SW9 0x0590
295#define SCB_Q_SW10 0x05A0
296#define SCB_Q_SW11 0x05B0
297#define SCB_Q_SW12 0x05C0
298#define SCB_Q_SW13 0x05D0
299#define SCB_Q_SW14 0x05E0
300#define SCB_Q_SW15 0x05F0
301#define SCB_Q_CLOCK 0x0600
302#define SCB_Q_INTER 0x0610
303#define SCB_Q_SYSERR 0x0620
304#define SCB_Q_PROCERR 0x0630
305#define SCB_Q_PWRFAIL 0x0640
306#define SCB_Q_PERFMON 0x0650
307#define SCB_Q_SYSMCHK 0x0660
308#define SCB_Q_PROCMCHK 0x0670
309#define SCB_Q_PASSREL 0x0680
310
311/*
312** Stack Frame (FRM) Offsets:
313**
314** There are two types of system entries for OSF/1 - those for the
315** callsys CALL_PAL function and those for exceptions and interrupts.
316** Both entry types use the same stack frame layout. The stack frame
317** contains space for the PC, the PS, the saved GP, and the saved
318** argument registers a0, a1, and a2. On entry, SP points to the
319** saved PS.
320*/
321
322#define FRM_Q_PS 0x0000
323#define FRM_Q_PC 0x0008
324#define FRM_Q_GP 0x0010
325#define FRM_Q_A0 0x0018
326#define FRM_Q_A1 0x0020
327#define FRM_Q_A2 0x0028
328
329#define FRM_K_SIZE 48
330
331#define STACK_FRAME(tmp1,tmp2) \
332 sll ps, 63-PS_V_CM, p7; \
333 bge p7, 0f; \
334 bis zero, zero, ps; \
335 mtpr sp, ptUsp; \
336 mfpr sp, ptKsp; \
3370: lda sp, 0-FRM_K_SIZE(sp); \
338 stq tmp1, FRM_Q_PS(sp); \
339 stq tmp2, FRM_Q_PC(sp); \
340 stq gp, FRM_Q_GP(sp); \
341 stq a0, FRM_Q_A0(sp); \
342 stq a1, FRM_Q_A1(sp); \
343 stq a2, FRM_Q_A2(sp)
344
345/*
346** Halt Codes:
347*/
348
349#define HLT_K_RESET 0x0000
350#define HLT_K_HW_HALT 0x0001
351#define HLT_K_KSP_INVAL 0x0002
352#define HLT_K_SCBB_INVAL 0x0003
353#define HLT_K_PTBR_INVAL 0x0004
354#define HLT_K_SW_HALT 0x0005
355#define HLT_K_DBL_MCHK 0x0006
356#define HLT_K_MCHK_FROM_PAL 0x0007
357
358/*
359** Machine Check Codes:
360*/
361
362#define MCHK_K_TPERR 0x0080
363#define MCHK_K_TCPERR 0x0082
364#define MCHK_K_HERR 0x0084
365#define MCHK_K_ECC_C 0x0086
366#define MCHK_K_ECC_NC 0x0088
367#define MCHK_K_UNKNOWN 0x008A
368#define MCHK_K_CACKSOFT 0x008C
369#define MCHK_K_BUGCHECK 0x008E
370#define MCHK_K_OS_BUGCHECK 0x0090
371#define MCHK_K_DCPERR 0x0092
372#define MCHK_K_ICPERR 0x0094
373#define MCHK_K_RETRY_IRD 0x0096
374#define MCHK_K_PROC_HERR 0x0098
375
376/*
377** System Machine Check Codes:
378*/
379
380#define MCHK_K_READ_NXM 0x0200
381#define MCHK_K_SYS_HERR 0x0202
382
383/*
384** Machine Check Error Status Summary (MCES) Register Format
385**
386** Extent Size Name Function
387** ------ ---- ---- ---------------------------------
388** <0> 1 MIP Machine check in progress
389** <1> 1 SCE System correctable error in progress
390** <2> 1 PCE Processor correctable error in progress
391** <3> 1 DPC Disable PCE error reporting
392** <4> 1 DSC Disable SCE error reporting
393*/
394
395#define MCES_V_MIP 0
396#define MCES_M_MIP (1<<MCES_V_MIP)
397#define MCES_V_SCE 1
398#define MCES_M_SCE (1<<MCES_V_SCE)
399#define MCES_V_PCE 2
400#define MCES_M_PCE (1<<MCES_V_PCE)
401#define MCES_V_DPC 3
402#define MCES_M_DPC (1<<MCES_V_DPC)
403#define MCES_V_DSC 4
404#define MCES_M_DSC (1<<MCES_V_DSC)
405
406#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
407 | MCES_M_DSC)
408
409/*
410** Who-Am-I (WHAMI) Register Format
411**
412** Extent Size Name Function
413** ------ ---- ---- ---------------------------------
414** <7:0> 8 ID Who-Am-I identifier
415** <15:8> 1 SWAP Swap PALcode flag - character 'S'
416*/
417
418#define WHAMI_V_SWAP 8
419#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP)
420#define WHAMI_V_ID 0
421#define WHAMI_M_ID 0xFF
422
423#define WHAMI_K_SWAP 0x53 /* Character 'S' */
424
425/*
426** Conventional Register Usage Definitions
427**
428** Assembler temporary `at' is `AT' so it doesn't conflict with the
429** `.set at' assembler directive.
430*/
431
432#define v0 $0 /* Function Return Value Register */
433#define t0 $1 /* Scratch (Temporary) Registers ... */
434#define t1 $2
435#define t2 $3
436#define t3 $4
437#define t4 $5
438#define t5 $6
439#define t6 $7
440#define t7 $8
441#define s0 $9 /* Saved (Non-Volatile) Registers ... */
442#define s1 $10
443#define s2 $11
444#define s3 $12
445#define s4 $13
446#define s5 $14
447#define fp $15 /* Frame Pointer Register, Or S6 */
448#define s6 $15
449#define a0 $16 /* Argument Registers ... */
450#define a1 $17
451#define a2 $18
452#define a3 $19
453#define a4 $20
454#define a5 $21
455#define t8 $22 /* Scratch (Temporary) Registers ... */
456#define t9 $23
457#define t10 $24
458#define t11 $25
459#define ra $26 /* Return Address Register */
460#define pv $27 /* Procedure Value Register, Or T12 */
461#define t12 $27
462#define AT $28 /* Assembler Temporary (Volatile) Register */
463#define gp $29 /* Global Pointer Register */
464#define sp $30 /* Stack Pointer Register */
465#define zero $31 /* Zero Register */
466
467/*
468** OSF/1 Unprivileged CALL_PAL Entry Offsets:
469**
470** Entry Name Offset (Hex)
471**
472** bpt 0080
473** bugchk 0081
474** callsys 0083
475** imb 0086
476** rdunique 009E
477** wrunique 009F
478** gentrap 00AA
479** dbgstop 00AD
480*/
481
482#define UNPRIV 0x80
483#define PAL_BPT_ENTRY 0x80
484#define PAL_BUGCHK_ENTRY 0x81
485#define PAL_CALLSYS_ENTRY 0x83
486#define PAL_IMB_ENTRY 0x86
487#define PAL_RDUNIQUE_ENTRY 0x9E
488#define PAL_WRUNIQUE_ENTRY 0x9F
489#define PAL_GENTRAP_ENTRY 0xAA
490
491#if defined(KDEBUG)
492#define PAL_DBGSTOP_ENTRY 0xAD
493/* #define NUM_UNPRIV_CALL_PALS 10 */
494#else
495/* #define NUM_UNPRIV_CALL_PALS 9 */
496#endif /* KDEBUG */
497
498/*
499** OSF/1 Privileged CALL_PAL Entry Offsets:
500**
501** Entry Name Offset (Hex)
502**
503** halt 0000
504** cflush 0001
505** draina 0002
506** cserve 0009
507** swppal 000A
508** rdmces 0010
509** wrmces 0011
510** wrfen 002B
511** wrvptptr 002D
512** swpctx 0030
513** wrval 0031
514** rdval 0032
515** tbi 0033
516** wrent 0034
517** swpipl 0035
518** rdps 0036
519** wrkgp 0037
520** wrusp 0038
521** rdusp 003A
522** whami 003C
523** retsys 003D
524** rti 003F
525*/
526
527#define PAL_HALT_ENTRY 0x0000
528#define PAL_CFLUSH_ENTRY 0x0001
529#define PAL_DRAINA_ENTRY 0x0002
530#define PAL_CSERVE_ENTRY 0x0009
531#define PAL_SWPPAL_ENTRY 0x000A
532#define PAL_WRIPIR_ENTRY 0x000D
533#define PAL_RDMCES_ENTRY 0x0010
534#define PAL_WRMCES_ENTRY 0x0011
535#define PAL_WRFEN_ENTRY 0x002B
536#define PAL_WRVPTPTR_ENTRY 0x002D
537#define PAL_SWPCTX_ENTRY 0x0030
538#define PAL_WRVAL_ENTRY 0x0031
539#define PAL_RDVAL_ENTRY 0x0032
540#define PAL_TBI_ENTRY 0x0033
541#define PAL_WRENT_ENTRY 0x0034
542#define PAL_SWPIPL_ENTRY 0x0035
543#define PAL_RDPS_ENTRY 0x0036
544#define PAL_WRKGP_ENTRY 0x0037
545#define PAL_WRUSP_ENTRY 0x0038
546#define PAL_RDUSP_ENTRY 0x003A
547#define PAL_WHAMI_ENTRY 0x003C
548#define PAL_RETSYS_ENTRY 0x003D
549#define PAL_RTI_ENTRY 0x003F
550
551#define NUM_PRIV_CALL_PALS 23
552
553#endif
554