1/*
2 * Copyright (c) 2003, 2004
3 * The Regents of The University of Michigan
4 * All Rights Reserved
5 *
6 * This code is part of the M5 simulator, developed by Nathan Binkert,
7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
9 * Schultz.
10 *
11 * Permission is granted to use, copy, create derivative works and
12 * redistribute this software and such derivative works for any purpose,
13 * so long as the copyright notice above, this grant of permission, and
14 * the disclaimer below appear in all copies made; and so long as the
15 * name of The University of Michigan is not used in any advertising or
16 * publicity pertaining to the use or distribution of this software
17 * without specific, written prior authorization.
18 *
19 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
20 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
21 * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
22 * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
24 * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
25 * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
26 * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
27 * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
28 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
29 */
30
31/*
32 * Copyright 1993 Hewlett-Packard Development Company, L.P.
33 *
34 * Permission is hereby granted, free of charge, to any person
35 * obtaining a copy of this software and associated documentation
36 * files (the "Software"), to deal in the Software without
37 * restriction, including without limitation the rights to use, copy,
38 * modify, merge, publish, distribute, sublicense, and/or sell copies
39 * of the Software, and to permit persons to whom the Software is
40 * furnished to do so, subject to the following conditions:
41 *
42 * The above copyright notice and this permission notice shall be
43 * included in all copies or substantial portions of the Software.
44 *
45 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
46 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
48 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
49 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
50 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
51 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
52 * SOFTWARE.
53 */
54
55#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
56#include "ev5_defs.h"
57#include "fromHudsonOsf.h" // OSF/1 specific definitions
58#include "fromHudsonMacros.h" // Global macro definitions
59
60/*
61 * args:
62 * a0: here
63 * a1: boot location
64 * a2: CSERVE_J_KTOPAL
65 * a3: restrart_pv
66 * a4: vptb
67 * a5: my_rpb
68 *
69 * SRM Console Architecture III 3-26
70 */
71
72 .global palJToSlave
73 .text 3
74palJToSlave:
75
76 ALIGN_BRANCH
77
78 bis a3, zero, pv
79 bis zero, zero, t11
80 bis zero, zero, ra
81
82 /* Point the Vptbr to a2 */
83
84 mtpr a4, mVptBr // Load Mbox copy
85 mtpr a4, iVptBr // Load Ibox copy
86 STALL // don't dual issue the load with mtpr -pb
87
88 /* Turn on superpage mapping in the mbox and icsr */
89 lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
90 STALL // don't dual issue the load with mtpr -pb
91 mtpr t0, mcsr // Set the super page mode enable bit
92 STALL // don't dual issue the load with mtpr -pb
93
94 lda t0, 0(zero)
95 mtpr t0, dtbAsn
96 mtpr t0, itbAsn
97
98 LDLI (t1,0x20000000)
99 STALL // don't dual issue the load with mtpr -pb
100 mfpr t0, icsr // Enable superpage mapping
101 STALL // don't dual issue the load with mtpr -pb
102 bis t0, t1, t0
103 mtpr t0, icsr
104
105 STALL // Required stall to update chip ...
106 STALL
107 STALL
108 STALL
109 STALL
110
111 ldq_p s0, PCB_Q_PTBR(a5)
112 sll s0, VA_S_OFF, s0 // Shift PTBR into position
113 STALL // don't dual issue the load with mtpr -pb
114 mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
115 STALL // don't dual issue the load with mtpr -pb
116 ldq_p sp, PCB_Q_KSP(a5)
117
118 mtpr zero, dtbIa // Flush all D-stream TB entries
119 mtpr zero, itbIa // Flush all I-stream TB entries
120
121 mtpr a1, excAddr // Load the dispatch address.
122
123 STALL // don't dual issue the load with mtpr -pb
124 STALL // don't dual issue the load with mtpr -pb
125 mtpr zero, dtbIa // Flush all D-stream TB entries
126 mtpr zero, itbIa // Flush all I-stream TB entries
127 br zero, 2f
128
129 ALIGN_BLOCK
130
1312: NOP
132 mtpr zero, icFlush // Flush the icache.
133 NOP
134 NOP
135
136 NOP // Required NOPs ... 1-10
137 NOP
138 NOP
139 NOP
140 NOP
141 NOP
142 NOP
143 NOP
144 NOP
145 NOP
146
147 NOP // Required NOPs ... 11-20
148 NOP
149 NOP
150 NOP
151 NOP
152 NOP
153 NOP
154 NOP
155 NOP
156 NOP
157
158 NOP // Required NOPs ... 21-30
159 NOP
160 NOP
161 NOP
162 NOP
163 NOP
164 NOP
165 NOP
166 NOP
167 NOP
168
169 NOP // Required NOPs ... 31-40
170 NOP
171 NOP
172 NOP
173 NOP
174 NOP
175 NOP
176 NOP
177 NOP
178 NOP
179
180 NOP // Required NOPs ... 41-44
181 NOP
182 NOP
183 NOP
184
185 hw_rei_stall // Dispatch to kernel
186