1#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
2#include "ev5_defs.h"
3#include "fromHudsonOsf.h" // OSF/1 specific definitions
4#include "fromHudsonMacros.h" // Global macro definitions
5#include "ev5_impure.h" // Scratch & logout area data structures
6#include "platform.h" // Platform specific definitions
7
8 .global palJToKern
9 .text 3
10palJToKern:
11/* Jump to kernel
12args:
13 Kernel address - a0
14 PCBB - a1
15 First free PFN - a3?
16
17 Enable kseg addressing in ICSR
18 Enable kseg addressing in MCSR
19 Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
20 Set PCBB -- pass pointer in arg
21 Set PTBR -- get it out of PCB
22 Set KSP -- get it out of PCB
23
24 Jump to kernel address
25
26 Kernel args-
27 s0 first free PFN
28 s1 ptbr
29 s2 argc 0
30 s3 argv NULL
31 s5 osf_param (sysconfigtab) NULL
32 */
33
34 ALIGN_BRANCH
35
36 ldq_p a0, 0(zero)
37 ldq_p a1, 8(zero)
38 ldq_p a3, 16(zero)
39
40#ifdef undef
41 LDLI(t0,0x200000000) // 8GB, like the Mikasa
42 LDLI(t0,0x40000000) // 1GB, like the SRM
43 STALL // don't dual issue the load with mtpr -pb
44#endif
45 /* Point the Vptbr at 8GB */
46 lda t0, 0x1(zero)
47 sll t0, 33, t0
48
49 mtpr t0, mVptBr // Load Mbox copy
50 mtpr t0, iVptBr // Load Ibox copy
51 STALL // don't dual issue the load with mtpr -pb
52
53 /* Turn on superpage mapping in the mbox and icsr */
54 lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
55 STALL // don't dual issue the load with mtpr -pb
56 mtpr t0, mcsr // Set the super page mode enable bit
57 STALL // don't dual issue the load with mtpr -pb
58
59 lda t0, 0(zero)
60 mtpr t0, dtbAsn
61 mtpr t0, itbAsn
62
63 LDLI (t1,0x20000000)
64 STALL // don't dual issue the load with mtpr -pb
65 mfpr t0, icsr // Enable superpage mapping
66 STALL // don't dual issue the load with mtpr -pb
67 bis t0, t1, t0
68 mtpr t0, icsr
69
70 STALL // Required stall to update chip ...
71 STALL
72 STALL
73 STALL
74 STALL
75
76 ldq_p s0, PCB_Q_PTBR(a1)
77 sll s0, VA_S_OFF, s0 // Shift PTBR into position
78 STALL // don't dual issue the load with mtpr -pb
79 mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
80 STALL // don't dual issue the load with mtpr -pb
81 ldq_p sp, PCB_Q_KSP(a1)
82
83 mtpr a0, excAddr // Load the dispatch address.
84 STALL // don't dual issue the load with mtpr -pb
85 bis a3, zero, a0 // first free PFN
86 ldq_p a1, PCB_Q_PTBR(a1) // ptbr
87 ldq_p a2, 24(zero) // argc
88 ldq_p a3, 32(zero) // argv
89 ldq_p a4, 40(zero) // environ
90 lda a5, 0(zero) // osf_param
91 STALL // don't dual issue the load with mtpr -pb
92 mtpr zero, dtbIa // Flush all D-stream TB entries
93 mtpr zero, itbIa // Flush all I-stream TB entries
94 br zero, 2f
95
96 ALIGN_BLOCK
97
982: NOP
99 mtpr zero, icFlush // Flush the icache.
100 NOP
101 NOP
102
103 NOP // Required NOPs ... 1-10
104 NOP
105 NOP
106 NOP
107 NOP
108 NOP
109 NOP
110 NOP
111 NOP
112 NOP
113
114 NOP // Required NOPs ... 11-20
115 NOP
116 NOP
117 NOP
118 NOP
119 NOP
120 NOP
121 NOP
122 NOP
123 NOP
124
125 NOP // Required NOPs ... 21-30
126 NOP
127 NOP
128 NOP
129 NOP
130 NOP
131 NOP
132 NOP
133 NOP
134 NOP
135
136 NOP // Required NOPs ... 31-40
137 NOP
138 NOP
139 NOP
140 NOP
141 NOP
142 NOP
143 NOP
144 NOP
145 NOP
146
147
148
149 NOP // Required NOPs ... 41-44
150 NOP
151 NOP
152 NOP
153
154 hw_rei_stall // Dispatch to kernel
155
156