TlmBridge.py (13821:f9252f27ded7) TlmBridge.py (13823:040971e0f728)
1# Copyright 2019 Google, Inc.
2#
3# Redistribution and use in source and binary forms, with or without
4# modification, are permitted provided that the following conditions are
5# met: redistributions of source code must retain the above copyright
6# notice, this list of conditions and the following disclaimer;
7# redistributions in binary form must reproduce the above copyright
8# notice, this list of conditions and the following disclaimer in the

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24# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25#
26# Authors: Gabe Black
27
28from m5.objects.SystemC import SystemC_ScModule
29from m5.params import *
30from m5.proxy import *
31
1# Copyright 2019 Google, Inc.
2#
3# Redistribution and use in source and binary forms, with or without
4# modification, are permitted provided that the following conditions are
5# met: redistributions of source code must retain the above copyright
6# notice, this list of conditions and the following disclaimer;
7# redistributions in binary form must reproduce the above copyright
8# notice, this list of conditions and the following disclaimer in the

--- 15 unchanged lines hidden (view full) ---

24# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25#
26# Authors: Gabe Black
27
28from m5.objects.SystemC import SystemC_ScModule
29from m5.params import *
30from m5.proxy import *
31
32class Gem5ToTlmBridge(SystemC_ScModule):
33 type = 'Gem5ToTlmBridge'
34 cxx_class = 'sc_gem5::Gem5ToTlmBridge'
32class Gem5ToTlmBridgeBase(SystemC_ScModule):
33 type = 'Gem5ToTlmBridgeBase'
34 abstract = True
35 cxx_class = 'sc_gem5::Gem5ToTlmBridgeBase'
35 cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
36
37 system = Param.System(Parent.any, "system")
38
39 gem5 = SlavePort('gem5 slave port')
40 tlm = MasterPort('TLM initiator socket')
41 addr_ranges = VectorParam.AddrRange([],
42 'Addresses served by this port\'s TLM side')
43
36 cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
37
38 system = Param.System(Parent.any, "system")
39
40 gem5 = SlavePort('gem5 slave port')
41 tlm = MasterPort('TLM initiator socket')
42 addr_ranges = VectorParam.AddrRange([],
43 'Addresses served by this port\'s TLM side')
44
44class TlmToGem5Bridge(SystemC_ScModule):
45 type = 'TlmToGem5Bridge'
46 cxx_class = 'sc_gem5::TlmToGem5Bridge'
45class TlmToGem5BridgeBase(SystemC_ScModule):
46 type = 'TlmToGem5BridgeBase'
47 abstract = True
48 cxx_class = 'sc_gem5::TlmToGem5BridgeBase'
47 cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
48
49 system = Param.System(Parent.any, "system")
50
51 gem5 = MasterPort('gem5 master port')
52 tlm = SlavePort('TLM target socket')
49 cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
50
51 system = Param.System(Parent.any, "system")
52
53 gem5 = MasterPort('gem5 master port')
54 tlm = SlavePort('TLM target socket')
55
56
57class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
58 type = 'Gem5ToTlmBridge32'
59 cxx_template_params = [ 'unsigned int BITWIDTH' ]
60 cxx_class = 'sc_gem5::Gem5ToTlmBridge<32>'
61 cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
62
63class Gem5ToTlmBridge64(Gem5ToTlmBridgeBase):
64 type = 'Gem5ToTlmBridge64'
65 cxx_template_params = [ 'unsigned int BITWIDTH' ]
66 cxx_class = 'sc_gem5::Gem5ToTlmBridge<64>'
67 cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
68
69
70class TlmToGem5Bridge32(TlmToGem5BridgeBase):
71 type = 'TlmToGem5Bridge32'
72 cxx_template_params = [ 'unsigned int BITWIDTH' ]
73 cxx_class = 'sc_gem5::TlmToGem5Bridge<32>'
74 cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
75
76class TlmToGem5Bridge64(TlmToGem5BridgeBase):
77 type = 'TlmToGem5Bridge64'
78 cxx_template_params = [ 'unsigned int BITWIDTH' ]
79 cxx_class = 'sc_gem5::TlmToGem5Bridge<64>'
80 cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'