25 26namespace tlm 27{ 28 29class tlm_dmi 30{ 31 public: 32 // Enum for indicating the access granted to the initiator. 33 // The initiator uses gp.m_command to indicate it intention (read/write) 34 // The target is allowed to promote DMI_ACCESS_READ or DMI_ACCESS_WRITE 35 // requests to dmi_access_read_write. 36 37 enum dmi_access_e { 38 DMI_ACCESS_NONE = 0x00, // no access 39 DMI_ACCESS_READ = 0x01, // read access 40 DMI_ACCESS_WRITE = 0x02, // write access 41 DMI_ACCESS_READ_WRITE = DMI_ACCESS_READ | DMI_ACCESS_WRITE 42 // read/write access 43 }; 44 45 tlm_dmi() { init(); } 46 47 void 48 init() 49 { 50 m_dmi_ptr = nullptr; 51 m_dmi_start_address = 0x0; 52 m_dmi_end_address = (sc_dt::uint64)(-1); 53 m_dmi_access = DMI_ACCESS_NONE; 54 m_dmi_read_latency = sc_core::SC_ZERO_TIME; 55 m_dmi_write_latency = sc_core::SC_ZERO_TIME; 56 } 57 58 unsigned char *get_dmi_ptr() const { return m_dmi_ptr; } 59 sc_dt::uint64 get_start_address() const { return m_dmi_start_address; } 60 sc_dt::uint64 get_end_address() const { return m_dmi_end_address; } 61 sc_core::sc_time get_read_latency() const { return m_dmi_read_latency; } 62 sc_core::sc_time get_write_latency() const { return m_dmi_write_latency; } 63 dmi_access_e get_granted_access() const { return m_dmi_access; } 64 bool is_none_allowed() const { return m_dmi_access == DMI_ACCESS_NONE; } 65 bool 66 is_read_allowed() const 67 { 68 return (m_dmi_access & DMI_ACCESS_READ) == DMI_ACCESS_READ; 69 } 70 bool 71 is_write_allowed() const 72 { 73 return (m_dmi_access & DMI_ACCESS_WRITE) == DMI_ACCESS_WRITE; 74 } 75 bool 76 is_read_write_allowed() const 77 { 78 return (m_dmi_access & DMI_ACCESS_READ_WRITE) == DMI_ACCESS_READ_WRITE; 79 } 80 81 void set_dmi_ptr(unsigned char *p) { m_dmi_ptr = p; } 82 void set_start_address(sc_dt::uint64 addr) { m_dmi_start_address = addr; } 83 void set_end_address(sc_dt::uint64 addr) { m_dmi_end_address = addr; } 84 void set_read_latency(sc_core::sc_time t) { m_dmi_read_latency = t; } 85 void set_write_latency(sc_core::sc_time t) { m_dmi_write_latency = t; } 86 void set_granted_access(dmi_access_e a) { m_dmi_access = a; } 87 void allow_none() { m_dmi_access = DMI_ACCESS_NONE; } 88 void allow_read() { m_dmi_access = DMI_ACCESS_READ; } 89 void allow_write() { m_dmi_access = DMI_ACCESS_WRITE; } 90 void allow_read_write() { m_dmi_access = DMI_ACCESS_READ_WRITE; } 91 92 private: 93 // If the forward call is successful, the target returns the dmi_ptr, 94 // which must point to the data element corresponding to the 95 // dmi_start_address. The data is organized as a byte array with the 96 // endianness of the target (endianness member of the tlm_dmi struct). 97 98 unsigned char *m_dmi_ptr; 99 100 // The absolute start and end addresses of the DMI region. If the decoder 101 // logic in the interconnect changes the address field e.g. by masking, the 102 // interconnect is responsible to transform the relative address back to an 103 // absolute address again. 104 105 sc_dt::uint64 m_dmi_start_address; 106 sc_dt::uint64 m_dmi_end_address; 107 108 // Granted access 109 110 dmi_access_e m_dmi_access; 111 112 // These members define the latency of read/write transactions. The 113 // initiator must initialize these members to zero before requesting a 114 // dmi pointer, because both the interconnect as well as the target can 115 // add to the total transaction latency. 116 // Depending on the 'type' attribute only one, or both of these attributes 117 // will be valid. 118 119 sc_core::sc_time m_dmi_read_latency; 120 sc_core::sc_time m_dmi_write_latency; 121}; 122 123} // namespace tlm 124 125#endif /* __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__ */
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