1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20#ifndef __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__
21#define __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__
22
| 1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20#ifndef __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__
21#define __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__
22
|
24
25namespace tlm
26{
27
28class tlm_dmi
29{
30 public:
31 // Enum for indicating the access granted to the initiator.
32 // The initiator uses gp.m_command to indicate it intention (read/write)
33 // The target is allowed to promote DMI_ACCESS_READ or DMI_ACCESS_WRITE
34 // requests to dmi_access_read_write.
35
36 enum dmi_access_e {
37 DMI_ACCESS_NONE = 0x00, // no access
38 DMI_ACCESS_READ = 0x01, // read access
39 DMI_ACCESS_WRITE = 0x02, // write access
40 DMI_ACCESS_READ_WRITE = DMI_ACCESS_READ | DMI_ACCESS_WRITE
41 // read/write access
42 };
43
44 tlm_dmi() { init(); }
45
46 void
47 init()
48 {
49 m_dmi_ptr = nullptr;
50 m_dmi_start_address = 0x0;
51 m_dmi_end_address = (sc_dt::uint64)(-1);
52 m_dmi_access = DMI_ACCESS_NONE;
53 m_dmi_read_latency = sc_core::SC_ZERO_TIME;
54 m_dmi_write_latency = sc_core::SC_ZERO_TIME;
55 }
56
57 unsigned char *get_dmi_ptr() const { return m_dmi_ptr; }
58 sc_dt::uint64 get_start_address() const { return m_dmi_start_address; }
59 sc_dt::uint64 get_end_address() const { return m_dmi_end_address; }
60 sc_core::sc_time get_read_latency() const { return m_dmi_read_latency; }
61 sc_core::sc_time get_write_latency() const { return m_dmi_write_latency; }
62 dmi_access_e get_granted_access() const { return m_dmi_access; }
63 bool is_none_allowed() const { return m_dmi_access == DMI_ACCESS_NONE; }
64 bool
65 is_read_allowed() const
66 {
67 return (m_dmi_access & DMI_ACCESS_READ) == DMI_ACCESS_READ;
68 }
69 bool
70 is_write_allowed() const
71 {
72 return (m_dmi_access & DMI_ACCESS_WRITE) == DMI_ACCESS_WRITE;
73 }
74 bool
75 is_read_write_allowed() const
76 {
77 return (m_dmi_access & DMI_ACCESS_READ_WRITE) == DMI_ACCESS_READ_WRITE;
78 }
79
80 void set_dmi_ptr(unsigned char *p) { m_dmi_ptr = p; }
81 void set_start_address(sc_dt::uint64 addr) { m_dmi_start_address = addr; }
82 void set_end_address(sc_dt::uint64 addr) { m_dmi_end_address = addr; }
83 void set_read_latency(sc_core::sc_time t) { m_dmi_read_latency = t; }
84 void set_write_latency(sc_core::sc_time t) { m_dmi_write_latency = t; }
85 void set_granted_access(dmi_access_e a) { m_dmi_access = a; }
86 void allow_none() { m_dmi_access = DMI_ACCESS_NONE; }
87 void allow_read() { m_dmi_access = DMI_ACCESS_READ; }
88 void allow_write() { m_dmi_access = DMI_ACCESS_WRITE; }
89 void allow_read_write() { m_dmi_access = DMI_ACCESS_READ_WRITE; }
90
91 private:
92 // If the forward call is successful, the target returns the dmi_ptr,
93 // which must point to the data element corresponding to the
94 // dmi_start_address. The data is organized as a byte array with the
95 // endianness of the target (endianness member of the tlm_dmi struct).
96
97 unsigned char *m_dmi_ptr;
98
99 // The absolute start and end addresses of the DMI region. If the decoder
100 // logic in the interconnect changes the address field e.g. by masking, the
101 // interconnect is responsible to transform the relative address back to an
102 // absolute address again.
103
104 sc_dt::uint64 m_dmi_start_address;
105 sc_dt::uint64 m_dmi_end_address;
106
107 // Granted access
108
109 dmi_access_e m_dmi_access;
110
111 // These members define the latency of read/write transactions. The
112 // initiator must initialize these members to zero before requesting a
113 // dmi pointer, because both the interconnect as well as the target can
114 // add to the total transaction latency.
115 // Depending on the 'type' attribute only one, or both of these attributes
116 // will be valid.
117
118 sc_core::sc_time m_dmi_read_latency;
119 sc_core::sc_time m_dmi_write_latency;
120};
121
122} // namespace tlm
123
124#endif /* __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__ */
| 25
26namespace tlm
27{
28
29class tlm_dmi
30{
31 public:
32 // Enum for indicating the access granted to the initiator.
33 // The initiator uses gp.m_command to indicate it intention (read/write)
34 // The target is allowed to promote DMI_ACCESS_READ or DMI_ACCESS_WRITE
35 // requests to dmi_access_read_write.
36
37 enum dmi_access_e {
38 DMI_ACCESS_NONE = 0x00, // no access
39 DMI_ACCESS_READ = 0x01, // read access
40 DMI_ACCESS_WRITE = 0x02, // write access
41 DMI_ACCESS_READ_WRITE = DMI_ACCESS_READ | DMI_ACCESS_WRITE
42 // read/write access
43 };
44
45 tlm_dmi() { init(); }
46
47 void
48 init()
49 {
50 m_dmi_ptr = nullptr;
51 m_dmi_start_address = 0x0;
52 m_dmi_end_address = (sc_dt::uint64)(-1);
53 m_dmi_access = DMI_ACCESS_NONE;
54 m_dmi_read_latency = sc_core::SC_ZERO_TIME;
55 m_dmi_write_latency = sc_core::SC_ZERO_TIME;
56 }
57
58 unsigned char *get_dmi_ptr() const { return m_dmi_ptr; }
59 sc_dt::uint64 get_start_address() const { return m_dmi_start_address; }
60 sc_dt::uint64 get_end_address() const { return m_dmi_end_address; }
61 sc_core::sc_time get_read_latency() const { return m_dmi_read_latency; }
62 sc_core::sc_time get_write_latency() const { return m_dmi_write_latency; }
63 dmi_access_e get_granted_access() const { return m_dmi_access; }
64 bool is_none_allowed() const { return m_dmi_access == DMI_ACCESS_NONE; }
65 bool
66 is_read_allowed() const
67 {
68 return (m_dmi_access & DMI_ACCESS_READ) == DMI_ACCESS_READ;
69 }
70 bool
71 is_write_allowed() const
72 {
73 return (m_dmi_access & DMI_ACCESS_WRITE) == DMI_ACCESS_WRITE;
74 }
75 bool
76 is_read_write_allowed() const
77 {
78 return (m_dmi_access & DMI_ACCESS_READ_WRITE) == DMI_ACCESS_READ_WRITE;
79 }
80
81 void set_dmi_ptr(unsigned char *p) { m_dmi_ptr = p; }
82 void set_start_address(sc_dt::uint64 addr) { m_dmi_start_address = addr; }
83 void set_end_address(sc_dt::uint64 addr) { m_dmi_end_address = addr; }
84 void set_read_latency(sc_core::sc_time t) { m_dmi_read_latency = t; }
85 void set_write_latency(sc_core::sc_time t) { m_dmi_write_latency = t; }
86 void set_granted_access(dmi_access_e a) { m_dmi_access = a; }
87 void allow_none() { m_dmi_access = DMI_ACCESS_NONE; }
88 void allow_read() { m_dmi_access = DMI_ACCESS_READ; }
89 void allow_write() { m_dmi_access = DMI_ACCESS_WRITE; }
90 void allow_read_write() { m_dmi_access = DMI_ACCESS_READ_WRITE; }
91
92 private:
93 // If the forward call is successful, the target returns the dmi_ptr,
94 // which must point to the data element corresponding to the
95 // dmi_start_address. The data is organized as a byte array with the
96 // endianness of the target (endianness member of the tlm_dmi struct).
97
98 unsigned char *m_dmi_ptr;
99
100 // The absolute start and end addresses of the DMI region. If the decoder
101 // logic in the interconnect changes the address field e.g. by masking, the
102 // interconnect is responsible to transform the relative address back to an
103 // absolute address again.
104
105 sc_dt::uint64 m_dmi_start_address;
106 sc_dt::uint64 m_dmi_end_address;
107
108 // Granted access
109
110 dmi_access_e m_dmi_access;
111
112 // These members define the latency of read/write transactions. The
113 // initiator must initialize these members to zero before requesting a
114 // dmi pointer, because both the interconnect as well as the target can
115 // add to the total transaction latency.
116 // Depending on the 'type' attribute only one, or both of these attributes
117 // will be valid.
118
119 sc_core::sc_time m_dmi_read_latency;
120 sc_core::sc_time m_dmi_write_latency;
121};
122
123} // namespace tlm
124
125#endif /* __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__ */
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