33a34,36
> #include "../core/scheduler.hh"
> #include "../dt/bit/sc_logic.hh"
> #include "../dt/bit/sc_lv.hh"
69c72
< write(const sc_dt::sc_lv<W> &)
---
> write(const sc_dt::sc_lv<W> &l)
71c74,83
< sc_channel_warn_unimpl(__PRETTY_FUNCTION__);
---
> ::sc_gem5::Process *p = ::sc_gem5::scheduler.current();
>
> auto it = inputs.find(p);
> if (it == inputs.end()) {
> inputs.emplace(p, l);
> this->request_update();
> } else if (it->second != l) {
> it->second = l;
> this->request_update();
> }
74c86
< operator = (const sc_dt::sc_lv<W> &)
---
> operator = (const sc_dt::sc_lv<W> &l)
76c88
< sc_channel_warn_unimpl(__PRETTY_FUNCTION__);
---
> write(l);
80c92
< operator = (const sc_signal_rv<W> &)
---
> operator = (const sc_signal_rv<W> &r)
82c94
< sc_channel_warn_unimpl(__PRETTY_FUNCTION__);
---
> write(r.read());
92c104,125
< sc_channel_warn_unimpl(__PRETTY_FUNCTION__);
---
> using sc_dt::Log_0;
> using sc_dt::Log_1;
> using sc_dt::Log_Z;
> using sc_dt::Log_X;
> static sc_dt::sc_logic_value_t merge_table[4][4] = {
> { Log_0, Log_X, Log_0, Log_X },
> { Log_X, Log_1, Log_1, Log_X },
> { Log_0, Log_1, Log_Z, Log_X },
> { Log_X, Log_X, Log_X, Log_X }
> };
>
> // Resolve the inputs, and give the result to the underlying
> // signal class.
> for (int i = 0; i < W; i++) {
> sc_dt::sc_logic_value_t bit = Log_Z;
> for (auto &input: inputs)
> bit = merge_table[bit][input.second.get_bit(i)];
> this->m_new_val.set_bit(i, bit);
> }
>
> // Ask the signal to update it's value.
> sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>::update();
99a133,134
>
> std::map<::sc_gem5::Process *, sc_dt::sc_lv<W> > inputs;