1/*
2 * Copyright 2018 Google, Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Gabe Black
28 */
29
30#ifndef __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RV_HH__
31#define __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RV_HH__
32
33#include "../core/sc_module.hh" // for sc_gen_unique_name
34#include "../core/scheduler.hh"
35#include "../dt/bit/sc_logic.hh"
36#include "../dt/bit/sc_lv.hh"
37#include "sc_signal.hh"
38
39namespace sc_dt
40{
41
42template <int W>
43class sc_lv;
44
45};
46
47namespace sc_core
48{
49
50class sc_port_base;
51
52template <int W>
53class sc_signal_rv : public sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>
54{
55 public:
56 sc_signal_rv() : sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>(
57 sc_gen_unique_name("signal_rv"))
58 {}
59 sc_signal_rv(const char *name) :
60 sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>(name)
61 {}
62 virtual ~sc_signal_rv() {}
63
64 virtual void register_port(sc_port_base &, const char *) {}
65
66 virtual void
67 write(const sc_dt::sc_lv<W> &l)
68 {
69 ::sc_gem5::Process *p = ::sc_gem5::scheduler.current();
70
71 auto it = inputs.find(p);
72 if (it == inputs.end()) {
73 inputs.emplace(p, l);
74 this->request_update();
75 } else if (it->second != l) {
76 it->second = l;
77 this->request_update();
78 }
79 }
80 sc_signal_rv<W> &
81 operator = (const sc_dt::sc_lv<W> &l)
82 {
83 write(l);
84 return *this;
85 }
86 sc_signal_rv<W> &
87 operator = (const sc_signal_rv<W> &r)
88 {
89 write(r.read());
90 return *this;
91 }
92
93 virtual const char *kind() const { return "sc_signal_rv"; }
94
95 protected:
96 virtual void
97 update()
98 {
99 using sc_dt::Log_0;
100 using sc_dt::Log_1;
101 using sc_dt::Log_Z;
102 using sc_dt::Log_X;
103 static sc_dt::sc_logic_value_t merge_table[4][4] = {
104 { Log_0, Log_X, Log_0, Log_X },
105 { Log_X, Log_1, Log_1, Log_X },
106 { Log_0, Log_1, Log_Z, Log_X },
107 { Log_X, Log_X, Log_X, Log_X }
108 };
109
110 // Resolve the inputs, and give the result to the underlying
111 // signal class.
112 for (int i = 0; i < W; i++) {
113 sc_dt::sc_logic_value_t bit = Log_Z;
114 for (auto &input: inputs)
115 bit = merge_table[bit][input.second.get_bit(i)];
116 this->m_new_val.set_bit(i, bit);
117 }
118
119 // Ask the signal to update it's value.
120 sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>::update();
121 }
122
123 private:
124 // Disabled
125 sc_signal_rv(const sc_signal_rv<W> &) :
126 sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>()
127 {}
128
129 std::map<::sc_gem5::Process *, sc_dt::sc_lv<W> > inputs;
130};
131
132} // namespace sc_core
133
134#endif //__SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RV_HH__