sc_signal.hh (13245:c666c5d4996b) | sc_signal.hh (13274:79ce1482d383) |
---|---|
1/* 2 * Copyright 2018 Google, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26 * 27 * Authors: Gabe Black 28 */ 29 30#ifndef __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_HH__ 31#define __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_HH__ 32 33#include <iostream> | 1/* 2 * Copyright 2018 Google, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26 * 27 * Authors: Gabe Black 28 */ 29 30#ifndef __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_HH__ 31#define __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_HH__ 32 33#include <iostream> |
34#include <sstream> |
|
34#include <string> 35#include <vector> 36 37#include "../core/sc_event.hh" 38#include "../core/sc_module.hh" // for sc_gen_unique_name 39#include "../core/sc_prim.hh" 40#include "../dt/bit/sc_logic.hh" 41#include "sc_signal_inout_if.hh" | 35#include <string> 36#include <vector> 37 38#include "../core/sc_event.hh" 39#include "../core/sc_module.hh" // for sc_gen_unique_name 40#include "../core/sc_prim.hh" 41#include "../dt/bit/sc_logic.hh" 42#include "sc_signal_inout_if.hh" |
42#include "warn_unimpl.hh" // for warn_unimpl | |
43 44namespace sc_core 45{ 46 47class sc_port_base; 48 49template <class T, sc_writer_policy WRITER_POLICY=SC_ONE_WRITER> 50class sc_signal : public sc_signal_inout_if<T>, 51 public sc_prim_channel 52{ 53 public: 54 sc_signal() : sc_signal_inout_if<T>(), 55 sc_prim_channel(sc_gen_unique_name("signal")), | 43 44namespace sc_core 45{ 46 47class sc_port_base; 48 49template <class T, sc_writer_policy WRITER_POLICY=SC_ONE_WRITER> 50class sc_signal : public sc_signal_inout_if<T>, 51 public sc_prim_channel 52{ 53 public: 54 sc_signal() : sc_signal_inout_if<T>(), 55 sc_prim_channel(sc_gen_unique_name("signal")), |
56 m_cur_val(T()), m_new_val(T()), _changeStamp(~0ULL) | 56 m_cur_val(T()), m_new_val(T()), _changeStamp(~0ULL), 57 _gem5Writer(NULL) |
57 {} 58 explicit sc_signal(const char *name) : 59 sc_signal_inout_if<T>(), sc_prim_channel(name), | 58 {} 59 explicit sc_signal(const char *name) : 60 sc_signal_inout_if<T>(), sc_prim_channel(name), |
60 m_cur_val(T()), m_new_val(T()), _changeStamp(~0ULL) | 61 m_cur_val(T()), m_new_val(T()), _changeStamp(~0ULL), 62 _gem5Writer(NULL) |
61 {} 62 explicit sc_signal(const char *name, const T &initial_value) : 63 sc_signal_inout_if<T>(), sc_prim_channel(name), | 63 {} 64 explicit sc_signal(const char *name, const T &initial_value) : 65 sc_signal_inout_if<T>(), sc_prim_channel(name), |
64 m_cur_val(initial_value), m_new_val(initial_value), _changeStamp(~0ULL) | 66 m_cur_val(initial_value), m_new_val(initial_value), 67 _changeStamp(~0ULL), _gem5Writer(NULL) |
65 {} 66 virtual ~sc_signal() {} 67 68 virtual void | 68 {} 69 virtual ~sc_signal() {} 70 71 virtual void |
69 register_port(sc_port_base &, const char *) | 72 register_port(sc_port_base &port, const char *iface_type_name) |
70 { | 73 { |
71 sc_channel_warn_unimpl(__PRETTY_FUNCTION__); | 74 if (WRITER_POLICY == SC_ONE_WRITER && 75 std::string(iface_type_name) == 76 typeid(sc_signal_inout_if<T>).name()) { 77 if (_gem5Writer) { 78 std::ostringstream ss; 79 ss << "\n signal " << "`" << name() << "' (" << 80 kind() << ")"; 81 ss << "\n first driver `" << _gem5Writer->name() << "' (" << 82 _gem5Writer->kind() << ")"; 83 ss << "\n second driver `" << port.name() << "' (" << 84 port.kind() << ")"; 85 SC_REPORT_ERROR( 86 "(E115) sc_signal<T> cannot have more than one driver", 87 ss.str().c_str()); 88 } 89 _gem5Writer = &port; 90 } |
72 } 73 74 virtual const T &read() const { return m_cur_val; } 75 operator const T&() const { return read(); } 76 77 virtual sc_writer_policy 78 get_writer_policy() const 79 { --- 71 unchanged lines hidden (view full) --- 151 // are not specified in the standard but are referred to directly by one 152 // of the tests. 153 T m_cur_val; 154 T m_new_val; 155 156 private: 157 sc_event _valueChangedEvent; 158 uint64_t _changeStamp; | 91 } 92 93 virtual const T &read() const { return m_cur_val; } 94 operator const T&() const { return read(); } 95 96 virtual sc_writer_policy 97 get_writer_policy() const 98 { --- 71 unchanged lines hidden (view full) --- 170 // are not specified in the standard but are referred to directly by one 171 // of the tests. 172 T m_cur_val; 173 T m_new_val; 174 175 private: 176 sc_event _valueChangedEvent; 177 uint64_t _changeStamp; |
178 sc_port_base *_gem5Writer; |
|
159 160 // Disabled 161 sc_signal(const sc_signal<T, WRITER_POLICY> &) : 162 sc_signal_inout_if<T>(), sc_prim_channel("") 163 {} 164}; 165 166template <class T, sc_writer_policy WRITER_POLICY> --- 7 unchanged lines hidden (view full) --- 174template <sc_writer_policy WRITER_POLICY> 175class sc_signal<bool, WRITER_POLICY> : 176 public sc_signal_inout_if<bool>, public sc_prim_channel 177{ 178 public: 179 sc_signal() : sc_signal_inout_if<bool>(), 180 sc_prim_channel(sc_gen_unique_name("signal")), 181 m_cur_val(bool()), m_new_val(bool()), | 179 180 // Disabled 181 sc_signal(const sc_signal<T, WRITER_POLICY> &) : 182 sc_signal_inout_if<T>(), sc_prim_channel("") 183 {} 184}; 185 186template <class T, sc_writer_policy WRITER_POLICY> --- 7 unchanged lines hidden (view full) --- 194template <sc_writer_policy WRITER_POLICY> 195class sc_signal<bool, WRITER_POLICY> : 196 public sc_signal_inout_if<bool>, public sc_prim_channel 197{ 198 public: 199 sc_signal() : sc_signal_inout_if<bool>(), 200 sc_prim_channel(sc_gen_unique_name("signal")), 201 m_cur_val(bool()), m_new_val(bool()), |
182 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL) | 202 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL), 203 _gem5Writer(NULL) |
183 {} 184 explicit sc_signal(const char *name) : 185 sc_signal_inout_if<bool>(), sc_prim_channel(name), 186 m_cur_val(bool()), m_new_val(bool()), | 204 {} 205 explicit sc_signal(const char *name) : 206 sc_signal_inout_if<bool>(), sc_prim_channel(name), 207 m_cur_val(bool()), m_new_val(bool()), |
187 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL) | 208 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL), 209 _gem5Writer(NULL) |
188 {} 189 explicit sc_signal(const char *name, const bool &initial_value) : 190 sc_signal_inout_if<bool>(), sc_prim_channel(name), 191 m_cur_val(initial_value), m_new_val(initial_value), | 210 {} 211 explicit sc_signal(const char *name, const bool &initial_value) : 212 sc_signal_inout_if<bool>(), sc_prim_channel(name), 213 m_cur_val(initial_value), m_new_val(initial_value), |
192 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL) | 214 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL), 215 _gem5Writer(NULL) |
193 {} 194 virtual ~sc_signal() {} 195 196 virtual void | 216 {} 217 virtual ~sc_signal() {} 218 219 virtual void |
197 register_port(sc_port_base &, const char *) | 220 register_port(sc_port_base &port, const char *iface_type_name) |
198 { | 221 { |
199 sc_channel_warn_unimpl(__PRETTY_FUNCTION__); | 222 if (WRITER_POLICY == SC_ONE_WRITER && 223 std::string(iface_type_name) == 224 typeid(sc_signal_inout_if<bool>).name()) { 225 if (_gem5Writer) { 226 std::ostringstream ss; 227 ss << "\n signal " << "`" << name() << "' (" << 228 kind() << ")"; 229 ss << "\n first driver `" << _gem5Writer->name() << "' (" << 230 _gem5Writer->kind() << ")"; 231 ss << "\n second driver `" << port.name() << "' (" << 232 port.kind() << ")"; 233 SC_REPORT_ERROR( 234 "(E115) sc_signal<T> cannot have more than one driver", 235 ss.str().c_str()); 236 } 237 _gem5Writer = &port; 238 } |
200 } 201 202 virtual const bool &read() const { return m_cur_val; } 203 operator const bool &() const { return read(); } 204 205 virtual sc_writer_policy 206 get_writer_policy() const 207 { --- 101 unchanged lines hidden (view full) --- 309 sc_event _valueChangedEvent; 310 sc_event _posedgeEvent; 311 sc_event _negedgeEvent; 312 313 uint64_t _changeStamp; 314 uint64_t _posStamp; 315 uint64_t _negStamp; 316 | 239 } 240 241 virtual const bool &read() const { return m_cur_val; } 242 operator const bool &() const { return read(); } 243 244 virtual sc_writer_policy 245 get_writer_policy() const 246 { --- 101 unchanged lines hidden (view full) --- 348 sc_event _valueChangedEvent; 349 sc_event _posedgeEvent; 350 sc_event _negedgeEvent; 351 352 uint64_t _changeStamp; 353 uint64_t _posStamp; 354 uint64_t _negStamp; 355 |
356 sc_port_base *_gem5Writer; 357 |
|
317 // Disabled 318 sc_signal(const sc_signal<bool, WRITER_POLICY> &) : 319 sc_signal_inout_if<bool>(), sc_prim_channel("") 320 {} 321}; 322 323template <sc_writer_policy WRITER_POLICY> 324class sc_signal<sc_dt::sc_logic, WRITER_POLICY> : 325 public sc_signal_inout_if<sc_dt::sc_logic>, public sc_prim_channel 326{ 327 public: 328 sc_signal() : sc_signal_inout_if<sc_dt::sc_logic>(), 329 sc_prim_channel(sc_gen_unique_name("signal")), 330 m_cur_val(sc_dt::sc_logic()), m_new_val(sc_dt::sc_logic()), | 358 // Disabled 359 sc_signal(const sc_signal<bool, WRITER_POLICY> &) : 360 sc_signal_inout_if<bool>(), sc_prim_channel("") 361 {} 362}; 363 364template <sc_writer_policy WRITER_POLICY> 365class sc_signal<sc_dt::sc_logic, WRITER_POLICY> : 366 public sc_signal_inout_if<sc_dt::sc_logic>, public sc_prim_channel 367{ 368 public: 369 sc_signal() : sc_signal_inout_if<sc_dt::sc_logic>(), 370 sc_prim_channel(sc_gen_unique_name("signal")), 371 m_cur_val(sc_dt::sc_logic()), m_new_val(sc_dt::sc_logic()), |
331 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL) | 372 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL), 373 _gem5Writer(NULL) |
332 {} 333 explicit sc_signal(const char *name) : 334 sc_signal_inout_if<sc_dt::sc_logic>(), sc_prim_channel(name), 335 m_cur_val(sc_dt::sc_logic()), m_new_val(sc_dt::sc_logic()), | 374 {} 375 explicit sc_signal(const char *name) : 376 sc_signal_inout_if<sc_dt::sc_logic>(), sc_prim_channel(name), 377 m_cur_val(sc_dt::sc_logic()), m_new_val(sc_dt::sc_logic()), |
336 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL) | 378 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL), 379 _gem5Writer(NULL) |
337 {} 338 explicit sc_signal(const char *name, 339 const sc_dt::sc_logic &initial_value) : 340 sc_signal_inout_if<sc_dt::sc_logic>(), sc_prim_channel(name), 341 m_cur_val(initial_value), m_new_val(initial_value), | 380 {} 381 explicit sc_signal(const char *name, 382 const sc_dt::sc_logic &initial_value) : 383 sc_signal_inout_if<sc_dt::sc_logic>(), sc_prim_channel(name), 384 m_cur_val(initial_value), m_new_val(initial_value), |
342 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL) | 385 _changeStamp(~0ULL), _posStamp(~0ULL), _negStamp(~0ULL), 386 _gem5Writer(NULL) |
343 {} 344 virtual ~sc_signal() {} 345 346 virtual void | 387 {} 388 virtual ~sc_signal() {} 389 390 virtual void |
347 register_port(sc_port_base &, const char *) | 391 register_port(sc_port_base &port, const char *iface_type_name) |
348 { | 392 { |
349 sc_channel_warn_unimpl(__PRETTY_FUNCTION__); | 393 if (WRITER_POLICY == SC_ONE_WRITER && 394 std::string(iface_type_name) == 395 typeid(sc_signal_inout_if<sc_dt::sc_logic>).name()) { 396 if (_gem5Writer) { 397 std::ostringstream ss; 398 ss << "\n signal " << "`" << name() << "' (" << 399 kind() << ")"; 400 ss << "\n first driver `" << _gem5Writer->name() << "' (" << 401 _gem5Writer->kind() << ")"; 402 ss << "\n second driver `" << port.name() << "' (" << 403 port.kind() << ")"; 404 SC_REPORT_ERROR( 405 "(E115) sc_signal<T> cannot have more than one driver", 406 ss.str().c_str()); 407 } 408 _gem5Writer = &port; 409 } |
350 } 351 352 virtual const sc_dt::sc_logic &read() const { return m_cur_val; } 353 operator const sc_dt::sc_logic &() const { return read(); } 354 355 virtual sc_writer_policy 356 get_writer_policy() const 357 { --- 101 unchanged lines hidden (view full) --- 459 sc_event _valueChangedEvent; 460 sc_event _posedgeEvent; 461 sc_event _negedgeEvent; 462 463 uint64_t _changeStamp; 464 uint64_t _posStamp; 465 uint64_t _negStamp; 466 | 410 } 411 412 virtual const sc_dt::sc_logic &read() const { return m_cur_val; } 413 operator const sc_dt::sc_logic &() const { return read(); } 414 415 virtual sc_writer_policy 416 get_writer_policy() const 417 { --- 101 unchanged lines hidden (view full) --- 519 sc_event _valueChangedEvent; 520 sc_event _posedgeEvent; 521 sc_event _negedgeEvent; 522 523 uint64_t _changeStamp; 524 uint64_t _posStamp; 525 uint64_t _negStamp; 526 |
527 sc_port_base *_gem5Writer; 528 |
|
467 // Disabled 468 sc_signal(const sc_signal<sc_dt::sc_logic, WRITER_POLICY> &) : 469 sc_signal_inout_if<sc_dt::sc_logic>(), sc_prim_channel("") 470 {} 471}; 472 473} // namespace sc_core 474 475#endif //__SYSTEMC_EXT_CHANNEL_SC_SIGNAL_HH__ | 529 // Disabled 530 sc_signal(const sc_signal<sc_dt::sc_logic, WRITER_POLICY> &) : 531 sc_signal_inout_if<sc_dt::sc_logic>(), sc_prim_channel("") 532 {} 533}; 534 535} // namespace sc_core 536 537#endif //__SYSTEMC_EXT_CHANNEL_SC_SIGNAL_HH__ |